Data Sheet

743
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Mode: DITH6
Name: CCBn
Offset: 0x70+n*0x4 [n=0..3]
Reset: 0x00000000
Property: -
z Bits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 23:6 – CCB[17:0]: Channel Compare/Capture Buffer Value
These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the
associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corre-
sponding CCBVx status bit.
The number of bits in this field corresponds to the size of the counter.
z Bits 5:0 – DITHERCYB[5:0]: Dithering Buffer Cycle Number
These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the CCx.DITHERCY bits on an UPDATE condition.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CCB[17:10]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CCB[9:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CCB[1:0] DITHERCYB[5:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000