Data Sheet

ManualsBrandsSeeedStudio ManualsMisc Single Board ComputersSeeedStudio ODYSSEY X86J4105800 Win10 Mini PC 8GB RAM

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

31.8.2.5 Device Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register

will also be reflected in the Interrupt Enable Set (INTENSET) register.

Name: INTENCLR

Offset: 0x14

Reset: 0x0000

Property: Write-Protected

z Bits 15:10 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to

zero when this register is written. These bits will always return zero when read.

z Bit 9 – LPMSUSP: Link Power Management Suspend Interrupt Enable

0: The Link Power Management Suspend interrupt is disabled.

1: The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated when the

Link Power Management Suspend interrupt Flag is set.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable the corre-

sponding interrupt request.

z Bit 8 – LPMNYET: Link Power Management Not Yet Interrupt Enable

0: The Link Power Management Not Yet interrupt is disabled.

1: The Link Power Management Not Yet interrupt is enabled and an interrupt request will be generated when the

Link Power Management Not Yet interrupt Flag is set.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the corre-

sponding interrupt request.

z Bit 7 – RAMACER: RAM Access Interrupt Enable

0: The RAM Access interrupt is disabled.

1: The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt

Flag is set.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt

request.

z Bit 6 – UPRSM: Upstream Resume Interrupt Enable

0: The Upstream Resume interrupt is disabled.

Bit151413121110 9 8

LPMSUSP LPMNYET

AccessRRRRRRR/WR/W

Reset00000000

Bit76543210

RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND

Access R/W R/W R/W R/W R/W R/W R R/W

Reset00000000