Data Sheet

793
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
31.8.3.2 EndPoint Status Clear Register n
Name:
EPSTATUSCLR
Offset: 0x104 + (x * 0x20)
Reset: 0x00
Property: Write-Protected
z Bit 7 – BK1RDY: Bank 1 Ready
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK1RDY bit.
z Bit 6 – BK0RDY: Bank 0 Ready
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK0RDY bit.
z Bit 5 – STALLRQ1:STALL bank 1 Request
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ1 bit.
z Bit 4 – STALLRQ0:STALL bank 0 Request
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ0 bit.
z Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 2 – CURBK: Current Bank
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.CURBK bit.
z Bit 1 – DTGLIN: Data Toggle IN
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.DTGLIN bit.
z Bit 0 – DTGLOUT: Data Toggle OUT
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the EPSTATUS.DTGLOUT bit.
Bit76543210
BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000