Data Sheet

808

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

31.8.4.5 Device Status Bank

Name:

STATUS_BK

Offset: 0x0A & 0x1A

Reset: 0xxxxxxxx

Property: NA

z Bits 7:2 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to

zero when this register is written. These bits will always return zero when read.

z Bit 1 – ERROFLOW: Error Flow Status

This bit defines the Error Flow Status.

0: No Error Flow detected.

1: A Error Flow has been detected.

This bit is set when a Error Flow has been detected during transfer from/towards this bank.

For OUT transfer, a NAK handshake has been sent.

For Isochronous OUT transfer, an overrun condition has occurred.

For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors.

z Bit 0 – CRCERR: CRC Error

This bit defines the CRC Error Status.

0: No CRC Error.

1: CRC Error detected.

This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.

Bit76543210

ERROFLOW CRCERR

Access R/W R/W R/W R/W R/W R/W R/W R/W

ResetXXXXXXXX