Data Sheet

817
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
31.8.5.7 Host Interrupt Enable Register Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x18
Reset: 0x0000
Property: Write-Protected
z Bits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 9 – DDISC: Device Disconnection Interrupt Enable
0: The Device Disconnection interrupt is disabled.
1: The Device Disconnection interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt.
z Bit 8 – DCONN: Device Connection Interrupt Enable
0: The Device Connection interrupt is disabled.
1: The Device Connection interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt.
z Bit 7 – RAMACER: RAM Access Interrupt Enable
0: The RAM Access interrupt is disabled.
1: The RAM Access interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt.
z Bit 6 – UPRSM: Upstream Resume from the device Interrupt Enable
0: The Upstream Resume interrupt is disabled.
1: The Upstream Resume interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt.
z Bit 5 – DNRSM: Down Resume Interrupt Enable
0: The Down Resume interrupt is disabled.
Bit151413121110 9 8
DDISC DCONN
AccessR/WRRRRRR/WR/W
Reset00000000
Bit76543210
RAMACER UPRSM DNRSM WAKEUP RST HSOF
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000