Datasheet

40.8.10 Host Control 1 Register
Name: HC1R
Offset: 0x28
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CARDDSEL CARDDTL DMASEL[1:0] HSEN DW LEDCTRL
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – CARDDSEL Card Detect Signal Selection
Note:
This register entry is specific to the SD/SDIO operation mode.
This bit selects the source for the card detection.
Value Description
0
The CD pin is selected.
1
The Card Detect Test Level (CARDDTL) is selected (for test purpose).
Bit 6 – CARDDTL Card Detect Test Level
Note:
This register entry is specific to the SD/SDIO operation mode.
This bit is enabled while the Card Detect Signal Selection (CARDDSEL) is set to 1 and it indicates
whether the card is inserted or not.
Value Description
0
No card.
1
Card inserted.
Bits 4:3 – DMASEL[1:0] DMA Select
One of the supported DAM modes can be selected. The user must check support of DMA modes by
referring the CA0R. Use of selected DMA is determined by DMA Enable (DMAEN) in TMR.
Value Name Description
0
SDMA SDMA is selected
1
Reserved Reserved
2
ADMA32 32-bit Address ADMA2 is selected
3
Reserved Reserved
Bit 2 – HSEN High Speed Enable
Before setting this bit, the user must check the High Speed Support (HSSUP) in CA0R.
If this bit is set to 0 (default), the peripheral outputs CMD line and DAT lines at the falling edge of the SD
clock (up to 25 MHz). If this bit is set to 1, the SDMMC outputs the CMD line and the DAT lines at the
rising edge of the SD clock (up to 50 MHz).
If Preset Value Enable (PVALEN) in HC2R is set to 1, the user needs to reset SD Clock Enable
(SDCLKEN) before changing this bit to avoid generating clock glitches. After setting this bit to 1, the user
sets SDCLEN to 1 again.
Value Description
0
Normal Speed mode.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1335