Datasheet

This bit can only be set to 1 if NISTER.BWRRDY is set to 1. An interrupt can only be generated if
NISIER.BWRRDY is set to 1.
Writing this bit to 1 clears this bit.
Value Description
0
Not ready to write buffer
1
Ready to write buffer
Bit 3 – DMAINT DMA Interrupt
This status is set if the peripheral detects the Host SDMA Buffer boundary during transfer. Refer to SDMA
Buffer Boundary (BOUNDARY) in BSR.
In case of ADMA, by setting the “int” field in the descriptor table, the peripheral rises this status flag when
the descriptor line is completed. This status flag does not rise after Transfer Complete (TRFC).
This bit can only be set to 1 if NISTER.DMAINT is set to 1. An interrupt can only be generated if
NISIER.DMAINT is set to 1.
Writing this bit to 1 clears this bit.
Value Description
0
No DMA Interrupt
1
DMA Interrupt
Bit 2 – BLKGE Block Gap Event
If the Stop At Block Gap Request (STPBGR) in BGCR is set to 1, this bit is set when either a read or a
write transaction is stopped at a block gap. If STPBGR is not set to 1, this bit is not set to 1.
In the case of a Read transaction:
This bit is set at the falling edge of the DAT Line Active (DLACT) status (when the transaction is stopped
at SD bus timing). The Read Wait must be supported in order to use this function. Refer to section “Read
Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” about the
detailed timing.
In the case of a Write transaction:
This bit is set at the falling edge of the Write Transfer Active (WTACT) status (after getting the CRC status
at SD bus timing). Refer to section “Write Transaction Wait / Continue Timing” in the “SD Host Controller
Simplified Specification V3.00” for more details on the sequence of events.
This bit can only be set to 1 if NISTER.BLKGE is set to 1. An interrupt can only be generated if
NISIER.BLKGE is set to 1.
Writing this bit to 1 clears this bit.
Value Description
0
No block gap event
1
Transaction stopped at block gap
Bit 1 – TRFC Transfer Complete
This bit is set when a read/write transfer and a command with Busy is completed.
In the case of a Read Transaction:
This bit is set at the falling edge of the Read Transfer Active Status. The interrupt is generated in two
cases. The first is when a data transfer is completed as specified by the data length (after the last data
has been read to the system). The second is when data has stopped at the block gap and completed the
data transfer by setting the Stop At Block Gap Request (STPBGR) in BGCR (after valid data has been
read to the system). Refer to section “Read Transaction Wait / Continue Timing” in the “SD Host
Controller Simplified Specification V3.00” for more details on the sequence of events.
In the case of a Write Transaction:
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1349