Datasheet

alarm, CTRLB.GPnEN must be written to zero and the associated COMPn/ALARMn must be written with
the correct value.
An example procedure to write the general purpose registers GP0 and GP1 is:
1. Wait for any ongoing write to COMP0 to complete (SYNCBUSY.COMP0 = 0). If the RTC is
operating in Mode 1, wait for any ongoing write to COMP1 to complete as well
(SYNCBUSY.COMP1 = 0).
2. Write CTRLB.GP0EN = 1 if GP0 is needed.
3. Write GP0 if needed.
4. Wait for any ongoing write to GP0 to complete (SYNCBUSY.GP0 = 0). Note that GP1 will also show
as busy when GP0 is busy.
5. Write GP1 if needed.
The following table provides the correspondence of General Purpose Registers and the COMPARE/
ALARM read or write buffer in all RTC modes.
Table 21-2. General Purpose Registers Versus Compare/Alarm Registers: n in 0, 2, 4, 6...
Register Mode 0 Mode 1 Mode 2 Write Before
GPn COMPn/2 write
buffer
(COMPn , COMPn
+1) write buffer
ALARMn/2 write
buffer
GPn+1
GPn+1 COMPn/2 read
buffer
(COMPn , COMPn
+1) read buffer
ALARMn/2 read
buffer
-
21.6.8.5 Tamper Detection
The RTC provides four tamper channels that can be used for tamper detection.
The action of each tamper channel is configured using the Input n Action bits in the Tamper Control
register (TAMPCTRL.INnACT):
• Off: Detection for tamper channel n is disabled.
• Wake: A transition on INn input (tamper channel n) matching TAMPCTRL.TAMPLVLn will be
detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will not be
captured in the TIMESTAMP register.
• Capture: A transition on INn input (tamper channel n) matching TAMPCTRL.TAMPLVLn will be
detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be
captured in the TIMESTAMP register.
• Active Layer Protection: A mismatch of an internal RTC signal routed between INn and OUTn pins
will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be
captured in the TIMESTAMP register.
In order to determine which tamper source caused a tamper event, the Tamper ID register (TAMPID)
provides the detection status of each tamper channel. These bits remain active until cleared by software.
A single interrupt request (TAMPER) is available for all tamper channels.
The RTC also supports an input event (TAMPEVT) for generating a tamper condition within the Event
System. The tamper input event is enabled by the Tamper Input Event Enable bit in the Event Control
register (EVCTRL.TAMPEVEI).
Up to four polarity external inputs (INn) can be used for tamper detection. The polarity for each input is
selected with the Tamper Level bits in the Tamper Control register (TAMPCTRL.TAMPLVLn).
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 293