Datasheet

To set TXGO, write a '1' to NCR.TSTART. Transmit halt does not take effect until any ongoing transmit
finishes.
If the DMA is configured for packet buffer Partial Store and Forward mode and a collision occurs during
transmission of a multi-buffer frame, transmission will automatically restart from the first buffer of the
frame. For packet buffer mode, the entire contents of the frame are read into the transmit packet buffer
memory, so the retry attempt will be replayed directly from the packet buffer memory rather than having to
re-fetch through the AHB.
If a used bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit
error. Transmission stops, GTXER is asserted and the FCS will be bad.
If transmission stops due to a transmit error or a used bit being read, transmission restarts from the first
buffer descriptor of the frame being transmitted when the transmit start bit is rewritten.
24.6.3.5 DMA Bursting on the AHB
The DMA will always use SINGLE, or INCR type AHB accesses for buffer management operations. When
performing data transfers, the AHB burst length is selected by the Fixed Burst Length for DMA Data
Operations bit field in the DMA Configuration register (DCFGR.FBLDO) so that either SINGLEor fixed
length incrementing bursts (INCR4, INCR8 or INCR16) are used where possible:
When there is enough space and enough data to be transferred, the programmed fixed length bursts will
be used. If there is not enough data or space available, for example when at the beginning or the end of a
buffer, SINGLE type accesses are used. Also SINGLE type accesses are used at 1024 Byte boundaries,
so that the 1 KByte boundaries are not burst over as per AHB requirements.
The DMA will not terminate a fixed length burst early, unless an error condition occurs on the AHB or if
receive or transmit are disabled in the Network Control register (NCR).
24.6.3.6 DMA Packet Buffer
The DMA uses packet buffers for both transmit and receive paths. This mode allows multiple packets to
be buffered in both transmit and receive directions. This allows the DMA to withstand far greater access
latencies on the AHB and make more efficient use of the AHB bandwidth. There are two modes of
operation—Full Store and Forward and Partial Store and Forward.
As described above, the DMA can be programmed into a low latency mode, known as Partial Store and
Forward. For further details of this mode, see the related Links.
When the DMA is in full store and forward mode, full packets are buffered which provides the possibility
to:
• Discard packets with error on the receive path before they are partially written out of the DMA, thus
saving AHB bus bandwidth and driver processing overhead,
• Retry collided transmit frames from the buffer, thus saving AHB bus bandwidth,
• Implement transmit IP/TCP/UDP checksum generation offload.
With the packet buffers included, the structure of the GMAC data paths is shown in this image:
SAM D5x/E5x Family Data Sheet
GMAC - Ethernet MAC
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 488