Datasheet

Reference Clock Switching
When a software operation requires reference clock switching, the normal operation is to disable the
DPLLn, modify the DPLLnCTRLB.REFCLK to select the desired reference source and activate the
DPLLn again. The CLK_DPLLn output clock is ready when DPLLnSTATUS.CLKRDY bit is set.
XOSC Reference Clock Divider
DPLLnCTRLB.DIV[10:0] bits are used to set the XOSC clock division factor and can be calculated with
following formula:

DIV
=
XOSC
2 ×
DIV + 1
For more information, refer to DPLLnCTRLB.
Loop Divider Ratio Updates
The DPLLn Controller supports on-the-fly update of the DPLLnRATIO register, so it is allowed to modify
the loop divider ratio and the loop divider ratio fractional part when the DPLLn is enabled. Ensure the
following conditions, or else the on-the-fly updating of the divider ratio will fail:
• DPLLnCTRLB.LBYPASS must be '0' (normal mode).
• DPLLnCTRLB.LTIME must not be 0x0, which is the default value.
• A DPLLn 32KHz clock (GCLK_DPLLn_32K) is configured in the GCLK peripheral as the internal lock
timer.
Write DPLLnRATIO.LDR[12:0] bits to set the integer part of the frequency multiplier, and write
DPLLnRATIO.LDRFRAC[4:0] bits to set the fractional part of the frequency multiplier. Due to
synchronization there is a delay between writing to DPLLnRATIO.LDRFRAC[4:0] or
DPLLnRATIO.LDR[12:0] and the effect on the DPLLn output clock. The value written
DPLLnRATIO.LDRFAC[4:0] or DPLLnRATIO.LDR[12:0] will be read back immediately, and the
DPLLRATIO bit in the synchronization busy register DPLLnSYNCBUSY.DPLLRATIO, will be set.
DPLLnSYNCBUSY.DPLLRATIO will be cleared when the operation is completed.STATUS.DPLLnLDRTO
is set when the DPLLnRATIO register has been modified and the DPLLn analog cell has successfully
sampled the updated value. At that time the DPLLnSTATUS.LOCK bit is cleared and set again by
hardware when the output frequency reached a stable state. Note that if only the fractional part of loop
divider ratio (DPLLnRATIO.LDRFRAC) is updated, the lock status (DPLLnSTATUS.LOCK) will not be
cleared.
Figure 28-7. RATIOCTRL register update operation
CKR
LDR
LDRFRAC
CK
CLK_DPLL
mult0
mult1
LOCK
LOCKL
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 776