Brochure

ESG
8.498.49
8.498.49
8.49
Sink
(0)
Source
(1)
V
CC
R2R1
R3
Q1
Q3
Q2
CR1
TTL-Gate
SSR
SSR
(1) 2,4 V
(0) 0,4 V
16 mA max.400 μA max.
Fig. 6: Typical circuit of a TTL gate driving SSR
a maximum 0.4 volt drop. Subtracting 0.4 volt from the
worst case Vcc of 4.5 volts, a minimum of 4.1 volts will
appear across the SSR input terminals, which is suf-
ficient to turn on most SSRs. For different supply
voltage tolerances, the values would be adjusted accor-
dingly.
With a negatively referenced SSR and the gate at logical
(1), Q1 conducts, but does not saturate, since it is opera-
ting as an emitter follower (common collector). In this
mode the gate can source up to 400 microamps; howe-
ver, the accumulated voltage drops are:
The sum of these values subtracted from the worst case
Vcc results in a minimum output voltage specified as 2.4
volts, which is 0.6 volt below the SSR turn-on threshold
(assuming a 3 volt turn-on). Although some SSRs may
operate satisfactorily in this mode, it is not recommen-
ded that this be done. Both the available current and the
minimum voltage are considered inadequate for the
typical optically isolated SSR.
It should be noted that the 2,4 volt gate output in the
logical 1 state relates only to a negatively referenced
load. It does not represent a voltage source to a positive-
ly referenced load (SSR), where it would appear to be
greater than the off state voltage. Referring again to Fig.
6, Q2 would be off and CR 1 is reverse biased, thus
presenting essentially an open circuit with virtually zero
potential across the SSR.
TTL drive methods
A standard TTL gate can drive most SSRs with ist 16 mA
sink capability. However, very few SSRs can be driven
reliably with the gates' available source current of only
400 μA. Also, the SSR minimum voltage threshold
requirements are not met in the source mode (i.e. gate
output in the positive leg of the SSR).
The relationship of the TTL gate to an SSR is illustrated
schematically in Fig. 6. In this configuration the SSR
supply voltage and the gate Vcc should be common and
comply with the TTL specified limits of say 5 volts +/-
10%. It can be seen that with a positively referenced SSR
and the gate at logical (0), Q2 is operating much like a
discrete NPN transistor in the grounded-emitter satura-
ted state. In this mode the gate can sink up to 16 mA with
R1
(IR Drop)
+ Q1
VBE
+ CR1
VF