User's Manual

Frequency selection of the receiver is accomplished with an independent synthesizer. Thus there are no RF
cables interconnecting the interrogation synthesizer and transmitter synthesizer. This also allows use of
commonly available IF filter products. The synthesizer output power is +17dBm in order to run a high IP3
mixer. A sampled output is provided on the front panel of the RTC Assembly for use with a frequency
counter. A divided output clock signal is also provided for integrity monitoring by the Monitor CCA.
From the first mixer the 125MHz IF signal is bandpass filtered using a Surface Acoustic Wave (SAW)
filter. Each SAW filter has approximately 825MHz bandwidth and provides excellent group delay flatness.
When cascaded, they also provide more than 90dB image rejection of the final 10.7 MHz IF. After the
SAW filter the IF signal is amplified then resistively split into the large signal and small signal path.
Each 125MHz path terminates with a log detector that provides almost 70dB of linear dynamic detection
range. Operational amplifiers provide the final gain before conversion of the detected signals by the dual
12-bit ADC at a sampling rate of 25MHz. The receiver dynamic range is greatly increased by using two
paths separated by approximately 25dB of signal strength. Internally the FPGA analyzes the two input
signal and determines which signal is best for timing reception.
Inside the Receiver FPGA located on the RTC CCA, the two detected signals are resampled at 50MHz then
low-pass filtered in order to reduce the noise bandwidth and eliminate the interpolated image. All of the
half amplitude detection, including a 2µs delay line, is accomplished digitally inside the Receiver FPGA.
This technique provides for superior receiver performance and stability.
For on-channel detection the large signal IF path is split before the log detector and down converted
separately to 10.7 MHz using a second mixer driven from a 114.3MHz oscillator. This final 10.7MHz IF is
narrow band filtered using cascaded ceramic filters then log detected. The resultant narrow-band signal is
compared against the detected large signal and used by the Receiver FPGA to insure that received pulses
are not from an adjacent DME channel.
1.3.2.5 Monitor Block Diagram Theory
Refer to Figure 1-10. The Monitor CCA performs supervision of critical DME/TACAN system parameters
and also performs self-monitoring. The Monitor CCA is actually two separate printed wiring boards but
they are plugged into each other; forming one module. The main board is dedicated mainly to digital
circuitry and is the card-cage support of the module, going from the back plane to the front panel. The
second board is dedicated to Interrogator (RF) circuitry.
The Monitor CCA is powered by a single +48V power supply coming from the back plane. Regulated
+1.2V, +2.5V, and +3.3V supplies are generated from the +48V by the Monitor CCA for the digital
circuitry. +5V regulated power is used for analog circuitry and +17V is used to power the Interrogator
board. The PS_OK LED is on while all the internal supplies are within limits. This LED can be also be
lighted by the ~TEST signal coming from the LCU.
The DSP coordinates all subsystems to measure the parameters, sends the measurements to the RMS using
RS232 communications, and notifies the LCU when a critical parameter is out of range using the primary
and secondary alarms. The DSP utilizes an external flash ROM for storage of the program and synchronous
dynamic RAM (SDRAM) as well as non-volatile RAM (NVRAM) for data storage. The DSP peripherals
include a voltage supervisor / watchdog, a dual UART, a programmable logic device with complex control
circuitry, and input / output latches.
The voltage supervisor / watchdog resets all the digital circuitry when the +3.3V power supply is too low,
when the LCU asserts the ~MRESET line, or when the DSP does not refresh the watchdog timer. The dual
UART is used to communicate with the RTC and the RMS through the back plane. The configuration
switches of the backplane determine if the Monitor is part of a high or low power DME; or if it’s in
TACAN mode. The ~LOCAL signal comes from the LCU and determines if the DME is being adjusted by
a local operator. The ~OVERLOAD signal comes from the Receiver/Transmitter Controllers (RTCs) and is
asserted when any RTC has reduced sensitivity because of the traffic load.