User's Manual

Model 1150A DVOR
2-56 Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
The U6 DSP communicates serially through one internal and two external UARTs (both in U25). The buffer circuit
U28 converts the TTL levels to and from RS232 levels (+8 to – 8 Volts Dc) using an internal power supply circuit.
The internal UART of U6 is connected to the factory debug port at J9. The other two UARTs control
communications to the RMS processor and provide a spare serial port.
The U6 DSP reads the operating frequency setting from the DIP switches on the backplane through the U47 buffer
circuit. When selected the A0 through A7 inputs from the backplane switch are presented to the bus. This
information is used to set the frequency of the Monitor synthesizer to a frequency that is 45 MHz less than the VOR
transmit frequency.
The U6 DSP reads the station configuration setting from the DIP switches on the backplane through the U46 buffer
circuit. When selected the A0 through A7 inputs from the backplane switch are presented to the bus. This
information is used to determine when the system is a DVOR or CVOR, single transmitter or dual and whether
adjustments can be made remotely or only locally. The ~LOCAL signal comes from the LCU and determines if the
VOR is being adjusted by a local operator.
The voltage supervisor / watchdog (U45) resets all the digital circuitry when the +3.3V power supply is too low,
when the LCU asserts the ~MRESET line, or when the U6 DSP does not refresh the watchdog timer.
The U6 DSP coordinates all subsystems to measure the parameters, sends the measurements to the RMS using
RS232 communications, and notifies the LCU (using latch U50) when a critical parameter is out of range using the
primary and secondary alarms. Front panel LEDs are controlled by the outputs of latch U52.
After a system reset, the alarm latch outputs (U50 and U52) are in the active state until updated by the DSP. The
alarms are updated only when the DSP refreshes the voltage supervisor / watchdog. If there is a DSP failure, the
alarms will remain in the last output state until watchdog time-out and the voltage supervisor / watchdog reset
activates the alarms. During normal operation, the alarm outputs are read by the DSP using an input buffer (U53) to
verify that outputs are not shorted or the latch has failed. The LEDs (CR12, CR14, CR16, CR18, and CR20) are
used to signal the alarms and pre-alarms conditions on the front panel. The CPU_OK LED (CR22) is used to
indicate that the U6 DSP is operating correctly. The external ~TEST signal coming from the LCU can light all LEDs
to verify they have not failed.
The U36 10MHz temperature-controlled crystal oscillator (TCXO) provides an accurate and reliable source of
timing for the digital circuitry sections.
Two BNC connectors are on the front panel. The SYNC signal is the trigger for an oscilloscope and the TEST signal
is the source signal for the oscilloscope. The PMDT can select which Test signal to display and the Master DSP
triggers the oscilloscope when the selected type is been sent
The Monitor provides the ability to measure the operating frequency of Transmitter 1 and Transmitter 2 carrier,
upper sideband and lower sideband. The signal “TMR1” is an input to the U6 DSP that has the ability to precisely
measure the frequency of the incoming signal. Circuits U19, U21, U63, U64 and U65 are programmable gates used
as multiplexers in this application. When control signal “SEL_FREQ_TX is low then the output of gate U21 is
selected which originates from transmitter 1. When control signal “SEL_FREQ_TX is high then the output of gate
U63 is selected which originates from transmitter 2. When control signal “SEL_FREQ_DIV1 is low then the output
of gates U19 and U64 are selected which originates from either the USB or LSB. When control signal
“SEL_FREQ_TX is high then the input 1_DIV_F0 of gate U21 and 2_DIV_F0 of gate U63 is selected which
originates from the carrier frequency source. When control signal “SEL_FREQ_DIV0, is low then the output of
gate U19 is the LSB (1_DIV_LSB) and the output of U64 is the LSB (2_DIV_LSB). When control signal
“SEL_FREQ_DIV0, is high then the output of gate U19 is the USB (1_DIV_USB) and the output of U64 is the
USB (2_DIV_USB).