User's Manual

Model 1150A DVOR
Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
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3.6.8.2.2
Monitor Test Results Screens
The Automatic Monitor Integrity Test feature uses the RMS processor to control the Test Generator in order validate
the Monitors ability to detect an out of tolerance condition. The Test Generator applies VOR composite signals to
the executive monitor channels on both Monitor 1 and Monitor 2 near the alarm limits to verify the ability of the
monitors to determine alarm conditions. If a monitor fails to detect an alarm for an out of tolerance parameter for
three consecutive tests
, it will be disabled from the monitor voting logic in the LCU and a monitor maintenance alert
will be generated. The Integrity Test runs continuously, starting a new test cycle approximately every 2 minutes.
For each test case, the RMS sets the test generator to the appropriate Low Test or High Test target value then the
Monitor samples the signal for display and comparison against the monitor Low and High Limits. If the monitor
finds that the Low Limit Low Test or High Limit High Test does not generate the appropriate monitor alarm
condition then that parameter is declared in alarm as shown with a red background. If the RMS finds that the Low
Limit High Test or High Limit Low Test generates a false monitor alarm condition then that parameter is declared in
alert as shown with a yellow background. The following formulas are used to determine the integrity test targets
based on the monitor lower alarm, nominal, and upper alarm limits:
• Low Limit Low Test: Lower Limit – (Nominal – Lower Limit)/10
• Low Limit High Test: Lower Limit + (Nominal – Lower Limit)/10
• High Limit Low Test: High Limit – (High Limit - Nominal)/10
• High Limit High Test: High Limit + (High Limit - Nominal)/10
When the RMS finds that a monitor declared an alarm when the test condition was inside the alarm limits then the
indication will be yellow (integrity alert). A disabled monitor is automatically re-enabled by the RMS following one
successful Monitor Integrity cycle. Failure of the Monitor Integrity test may be caused by improper set up of the
Monitor 1/2>>Offsets and Scale Factors>> Test Generator Certification settings.
When a monitor is disabled from the monitor voting logic in the LCU, a red Integrity Test Failed indicator is shown
on the RMS >> Data >> Maintenance Alert/Alarms screen (Figure 3-10).
As an additional integrity check, the RMS verifies that the each monitor completes the integrity test cycle within a
10 minute period. Failure to complete all tests within this period results in disabling the monitor.