User's Manual

Model 1150A DVOR
2-12 Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
While serving as an interconnect board, the 012262 CCA also contains a temperature sensor, U12 and an EEPROM,
U10. These are serial interface circuits that use a port expander, U9 digital gates to select the devices. The port
expander U9 along with U8:B, U11, U13, and U14 allows serial communication using a single chip select signal.
U1, U2, U7, U8:A, U21, and U22 are buffers for the digital signals coming into the 012262 CCA. L4 and C59 serve
as a filter on the reset line for the digital circuits. U18 and U23 function as a window comparator for the power
supply voltages. CR19 is a visual indicator on the front panel of the synthesizer assembly to display the status of the
voltages monitored by the window comparator circuit.
Figure 2-6 Carrier Phase Control Loop
2.3.2.1.2.3
Carrier Phase Control Loop
Refer to Figure 2-6, Carrier Phase Control Loop Block Diagram. RF from the carrier frequency PLL synthesizer is
applied to buffer amplifier U18, and then routed to the reference phase input of phase detector hybrid HY1.
The VOR system takes a sample of the carrier transmitter output from the carrier amplifier assembly. This sample
of the modulated carrier output signal is brought into the 030838 Synthesizer Assembly via connector J3 on the back
panel. The signal passes through limiter hybrid HY2, which serves to remove the 30 percent amplitude modulation,
but leaving the phase distortion information intact. This limited signal then goes through buffer amplifier U20, a
phase shift network consisting of C82, C84, C86, L23 and L26. This phase shift network provides approximately
180 degrees of RF phase shift to the signal. The signal is then applied to the variable phase input of phase detector
HY1.