User's Manual

Model 1150A DVOR
2-14 Rev. - November, 2008
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The output of T4 is then routed to buffer amplifier U21. Amplifier U21 feeds signal to the carrier amplifier in the
VOR system. C102 couples a small RF sample from the output of U21 and is sent to the detector U22 and a buffer
amplifier for monitoring of the output power to the carrier amplifier. U22 is a detector integrated circuit that
generates a voltage on the output proportional to the RF input power. There is sufficient gain compression in U21 to
minimize any changes in attenuation due to the small changes in loss of the phaser network with varying control
voltage.
U17, R76, and R77 are used to provide a DC offset in the output of U13:A. This offset is adjusted so that the error
voltage seen at the phase control loop integrator U15 output is a nominal zero volts, maximizing the useful control
range of U15. This error voltage is available at a test point (TP1) on the front panel of the synthesizer module. U17
is a digital potentiometer that requires the use of the SPI bus from the audio generator and software to program the
part. U17 is adjusted to set the phase error voltage as measured at TP1 to a nominal zero volts, +/- 0.050 volts when
the synthesizer module is installed in the VOR system cabinet.
Note that in some cases, due to the large available phase shift of the phaser network (>450 degrees) U17 can be
adjusted to achieve zero volts at TP1 at two separate points. The actual phase loop control voltage (output of
U13:A) is measured at TP2 on the synthesizer front panel. U17 should be adjusted with the use of software to
provide zero volts error voltage at TP1 between 2 and 8 volts as seen at TP2. If a zero volt phase error is achieved
below 2 volts or above 8 volts, re-adjust U17 to see if a lock condition can be found between these two points.
Figure 2-7 Sideband RF Generation Loop
2.3.2.1.2.4
Sideband RF Generation Loops
The block diagram in Figure 2-7 depicts the sideband loop. Refer to Figure 2-7, Sideband RF Generation Loop.
The synthesizer CCA (012258) within the synthesizer module generates the sideband signals necessary for CVOR or
DVOR system configuration. Connector J3 provides the input RF signal from the carrier CCA (012263) within the
synthesizer assembly. From the J3 connection RF is routed through a resistive attenuator (R1, R2, R3). The
attenuator provides a resistive load to the U21 amplifier from the carrier CCA (012263). U1 is a buffer amplifier
used to amplify the input signal and to provide isolation between the carrier CCA and the sideband CCA.