User's Manual

Model 1150A DVOR
2-16 Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
All signals and power supplies of the Audio Generator CCA enter and exit through right-angle DIN connectors P1
and P2; which connect to the Control Backplane CCA. Digital Signal Processor (DSP) U6 communicates to the
RMS CCA through UART U12 and TTL-RS232 converter U14. Oscillator Y1 clocks the DSP U6 while uP
supervisor U13 monitors the watchdog strobe, external ~MRESET, and on-board power; resetting DSP U6 if
necessary. DSP U6 utilizes memory which includes flash ROM U1 / U2, synchronous DRAM U4, and non-volatile
RAM U3.
DSP U6 also has serial ports available at debug header JP1 and spare header JP2 that are only used at the factory.
Configuration switches on the Control Backplane CCA are read by DSP U6 through buffers U29 and U30.
Synthesizer and sideband digital I/O is controlled through latch U27 and SPI / SPORT buffers U28 and U24.
Coder / Decoder (CODEC) U51 contains two analog-to-digital (ADC) converters and two digital-to-analog (DAC)
converters. One ADC / DAC pair is used for voice and ident processing while the other ADC converts over 24
channels of powers, phases, and audio levels switched through multiplexers U54 and U48. CODEC U51 responds to
DSP U6 SPORT and Timer2 controls.
Channel selection of Multiplexers U54 and U48 is controlled by DSP U6 through programmable logic device (PLD)
U40.
DSP U6 also has direct read / write access to the 32Kx16 of carrier audio RAM (CARRAM) U41 and U42 as well
as the 32Kx16 of sideband audio RAM (SBRAM) U43 and U45 through PLD U40. Once the CARRAM and
SBRAM have been initialized, DSP U6 can command PLD U40 to cycle through the contents of the RAM at a rate
determined by oscillator Y2.
The contents of the CARRAM are transferred to carrier DAC U44 as reference modulation while the contents of the
SBRAM are clocked into SB1/3 DACs U18 and SB2/4 DACs U20 as audio outputs. The power levels of DACs
U44, U18, and U20 are set by DACs U31 and U32. DACs U31, U32, and U33 are directly written by DSP U6.
DACs U32 and U33 establish sideband and carrier phase control.
PLD U40 offsets the CARRAM addresses by 7.5 degrees if appropriately strapped at header JP3 and ground-check
commanded by the Monitor CCA. PLD U40 synchronizes its internal audio RAM counters to that of the other Audio
Generator CCA if logic U19 and U39 indicate that this Audio Generator CCA is not actively on the antenna and a
new cycle is beginning.
The DVOR / ~CVOR configuration input of PLD U40-126 determines if the SB1/3 and SB2/4 bi-phase signals
repeat at 720 or 30 hertz rates. Both of these outputs from PLD U40-19 and U40-18 are buffered by U25-8 and U25-
9 as SIN_BIPHS and COS_BIPHS.
Commutator switch controls DVSC0 through DVSC5 are generated by PLD U40 during audio RAM cycling. They
are converted from digital to RS422 levels by U21 and U22. DVSC5 is also buffered by U46 and presented to the
front panel as SYNC on test point TP3.