User's Manual

Model 1150A DVOR
Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
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Two types of over-voltage protection are utilized for DC-DC converter U10. SCR Q1 in conjunction with CR7, R33,
R
28, and C30 will activate and open fuse F1 if the output voltage exceeds approximately +6.8VDC. Zener diode
CR8 provides redundant over-voltage protection.
The +5VDC supply powers linear regulator U11, which creates the +3.3VDC output. The +3.3VDC output is
measurable on test point TP12 and is filtered by capacitor C36.
The +5VDC supply also feeds the U13 DC-DC converter to generate -5VDC. Capacitor C44, inductor L4, and
capacitor C46 filter the -5VDC output, which is measurable at test point TP14.
LED_PWR, which originates at the diode-OR’d junction of diodes CR3 and CR4, sources zener diode CR10
through current-limit resistors R39 and R40 to create a precision +10VDC that can be measured at test point TP16.
The precision +10VDC powers “window” comparators U19:A and U19:B; which compare the +5VDC voltage at
U19-4 and U19-7 to the trip points established by resistors R42, R43, and R44 at U19-5 and U19-6.
The precision +10VDC also powers “window” comparators U19:C and U19:D; which compare the +3.3VDC at
U19-8 and U19-11 to the trip points established by resistors R45, R46, and R47 at U19-9 and U19-10.
The precision +10VDC also powers “window” comparators U20:C and U20:D; which compare the -5VDC scaled
by resistors R51 and R52 at U20-8 and U20-11 to the trip points established by resistors R48, R49, and R50 at U20-
9 and U20-10.
While the +5VDC, +3.3VDC, and -5VDC supplies are within the “window” trip points, the U19-2, U19-1, U19-14,
U19-13, U20-14, and U20-13 comparator outputs will be pulled-up to +10VDC through resistor R53; presenting a
higher level on U20-4 and U20-6 than that presented by the R54 and R55 voltage-divided +10VDC on U20-5 and
U20-7. Thus the U20-2 and U20-1 outputs go low. A low on U20-2 lights the CR11 PWR_OK LED through
current-limit resistor R56 and voltage-limit zener diode CR12. A low on U20-1 pulls the ~TGEN_OK signal low,
assuming a pull-up resistor after connector P2:A7 at the Facilities CCA.
If any of the +5VDC, +3.3VDC, or -5VDC supplies go above or below the “window” trip points, both U20:A and
U20:B comparator outputs de-assert; darkening the CR11 PWR_OK LED and causing the ~TGEN_OK signal to go
high, assuming a pull-up resistor after connector P2:A7 at the Facilities CCA.
The ~TEST signal from connector P2:B8, when active low, is guaranteed to light the CR11 PWR_OK LED through
diode CR13.
The U1 PLD is factory-programmed via ISP connector J3 and clocked by the 19.6608MHz oscillator Y1. Reset
supervisor U3 will reset the U1 PLD if one of three events occurs; the +3.3VDC supply drops too low, an external
reset (~MREST) is asserted from connector P1:B16, or the watchdog signal at U3-6 becomes too slow. The
watchdog signal is also buffered by U2 and presented as 30Hz SYNCH on front panel test point TP1.
The test generator waveforms are serially loaded into the U1 PLD by the primary and secondary transmit SPORT
signals TSCLK1, DT1PRI, DT1SEC, and TFS1. These signals originate at the RMS CCA, enter via connector P2,
are buffered by U18, and connect to PLD U1. The test generator data is serially echoed back to the RMS CCA for
error-checking by the primary and secondary receive SPORT signals DR1PRI and DR1SEC, also buffered by U18
before exiting connector P2.
The U1 PLD constructs parallel data from the SPORT serial streams and stores the results in the 32Kx16 locations
of SRAM U4 and U5. After all waveform data is saved, the U1 PLD cycles through all 32K locations at a 30Hz rate
while also clocking D-A converter U6. Thus the digital data is converted to an analog test generator waveform at
U6-22, amplified and filtered by U7:A, and presented to front panel test point TP5 as TGEN+.
Analog drivers U8:B, U7:B, U9:A, and U9:B create differential test generator waveform signals which exit via
connector P1 and eventually connect to the Monitor CCAs for certification.