User's Manual

Table Of Contents
Model 1150A DVOR
2-54 Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
Figure 2-20 Monitor CCA, Block Diagram
MOSI
BF2
MODE = 10
SPI Slave Boot
`
AD9241AS
IF ADC
PPI0..13(PF6)
TIMER0
PPI_CLK
AUDIO DAC 1
SPORT0 CLK
SPORT0 PRI XMT
SPORT0 TFS
MISO
PF1 (HWAIT)
MOSI
/SPI_SS/PF0
SPICLK
MISO
PF12 (HWAIT)
SPICLK
MOSI
PF3 /BF2_CS
SPORT1 CLK
SPORT1 RCV
SPORT1 TFS
SPORT1 XMT
SPORT1 CLK
SPORT1 RCV
SPORT1 RFS
SPORT1 XMT
10K
PF2
PF3
Test Point
Test Point
DBG TX
DBG RX
RS-232
Line Driver
4-Pin
Header
UART
1 MB NOR
FLASH
(DSP1 and
DSP2 Code)
32K NVARM
SPI ADC
32 MB SDRAM
Parallel Bus
SPORT0 SEC XMT
AUDIO DAC 2
PF1 /ADC_SLOW_CS
Configuration
Registers
ALARM and
Indicators
125 KHz IF
Detected Voice+IDENT
Detected IDENT
PF4 PF4
DVSC5 Commutaor SYCN
RS-232
Line Driver
4-Pin
Header
DBG TX
DBG RX
ADC
Mux
Test Generator
Standby RF detector
IF Baseband Samples
400 KHz Sample Clock
Sampled IF
Sampled Test Generator/
Sampled Standby Detected RF
RMS
SERIAL
INTERFACE
LCU
ALARMS
Receiver
Field Monitor
Antenna