Data Sheet
Table Of Contents
- Datasheet
- Preface
- About this Datasheet
- Product Features
- Regulatory Approval
- Physical Characteristics
- 3.1 ECCN and Part Number
- 3.2 Electrical Operating Conditions
- 3.3 Environmental Operating Conditions
- 3.4 Auxiliary ADC Specification
- 3.5 Power Supply Dimensioning
- 3.6 I/O Characteristics
- 3.7 Package Description
- 3.8 Packing Information
- 3.9 Storage Conditions
- 3.10 Mounting Considerations
- 3.11 Component Reliability
- 3.12 RF Performance
- Signals and Pins
- Acronyms
SIGNALS AND PINS
NOTES ON SP150Q SIGNALS
SP150Q DATASHEET PROPRIETARY 36
SEQUANS Communications
4.2.2 I2S/PCM Interface Signals
• PCM_RXD: PCM receive data. PCM data block is 8-bits or 16-bits. Only one
data block is received per frame. Receive time-slot offset is programmable
by using the RX_SLOT register. For instance, if RX_SLOT=5, then the 8-bit
data block is received from time-slot #5 to #12. Bit-order is configurable.
• PCM_CLK: PCM clock input, from 128 kHz to 8192 kHz
Sequans PCM interface takes PCM_CLK as an input in both master and
slave modes.
Caution: This clock signal is an input in both master and slave modes.
When choosing a clock source for PCM_CLK, it is important to ensure that
the selected frequency is supported by the IC connected to SP150Q's PCM
interface.
The choice of frequency depends on:
– Sampling frequency Fs
– Number of bits per sample Nbps
– Number of slots per PCM frame
It is given by the following formula:
PCM_CLK = Fs * Nbps * slots-per-PCM-frame
Where SP150Q supports:
– All commonly used sampling frequencies (8 kHz, 16 kHz, 32 kHz, 44.1
kHz, 48 kHz, 96 kHz, 192 kHz, 22.05 kHz, 44.1 kHz, 88.2 kHz, 176.4
kHz)
– 8 or 16 bits per sample (Nbps)
– 1 to (1024/Nbps) slots per PCM frame
• PCM_FS: Frame synchronization at 8 kHz. The number of time-slots within
a frame varies, depending on PCM_CLK frequency. To be flexible in offset
configuration, we define one PCM clock period per time-slot. Therefore, in
8-bit format, 8 time-slots are used to receive or transmit one 8-bit data
block. If PCM_CLK=128 kHz, there are 16 time-slots per frame. If
PCM_CLK=8192 kHz, there are 1024 time-slots per frame. In master mode,
PCM_FS is an output generated internally. In slave mode, PCM_FS is an
input. Both short and long Frame Sync standards are supported. Short
Frame Sync is high for one and only one PCM clock period. Long Frame
Sync is high for three consecutive PCM clock periods. In both cases, the
positive edge of PCM_FS occurs every 125 µs.
• PCM_TXD: PCM transmit data. PCM data block is 8-bits or 16-bits. Only
one data block is transmitted per frame. Transmit time-slot offset is
programmable by using the TX_SLOT register. For instance, if TX_SLOT=8,
then the 8-bit data block is transmitted from time-slot #8 to #15. Bit-order is
configurable. PCM_TXD is in low-impedance during data transmission,
otherwise it is in high impedance.