Specifications

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© 2003 SGC Inc. 52
the input impedance with input capacitance until a
low VSWR is measured of less than 2:1. This
process will continue until the VSWR has climbed
back to higher than 2:1 or the impedance has become
high.
5. The settings that gave the lowest VSWR have been
kept in memory and are now recalled to verify it is a
low VSWR
6. At this point the tune indicators are engaged. The
current relay data is saved if JP3 is set to tune from
memory; if JP1 is set to tune elements out during
receive position, the program waits until forward
power is no longer present, then removes all tuning
elements. The frequency is saved for future
frequency comparison, and the computer reverts to
Stop mode.