Specifications

L506 Hardware Design
Copyright© Shanghai Mobiletek Communication Ltd 34
Figure 3-9 L506 to codec module timing
Table 3-12 PCM interface Timing
Parameter
Descriptions
DC characters
Min.
Typ.
Max.
Unit
T(sync)
PCM_SYNC cycle
-
125
-
us
T(synch)
PCM_SYNC high level hold
time
-
488
-
ns
T(syncl)
PCM_SYNC low level hold
time
-
124.5
-
us
T(clk)
PCM_CLK cycle
-
488
-
ns
T(clkh)
PCM_CLK high level hold
time
-
244
-
ns
T(clkl)
PCM_CLK low level hold time
-
244
-
ns
T(susync)
PCM_SYNC establish time
-
122
-
ns
T(hsync)
PCM_SYNC hold time
-
366
-
ns
T(sudin)
PCM_IN establish time
60
-
-
ns
T(hdin)
PCM_IN hold time
60
-
-
ns
T(pdout)
From PCM_CLK rising edge to
PCM_OUTvalid time
-
-
60
ns
T(zdout)
From PCM_CLK falling edge
to PCM_OUT high
impendence delay time
-
-
60
ns