Data Sheet
Table Of Contents
- Abstract
- 1. Introduction
- 2. Characteristic
- 3. Pin Definition
- 4. System memory space
- 5. ATE（RF Test Mode）
- 5.1. ATE Command
- 5.1.1. Start MP mode
- 5.1.2. Stop MP mode
- 5.1.3. Set Tx rate
- 5.1.4. Set operational channel
- 5.1.5. Set operational bandwidth
- 5.1.6. Set Tx power
- 5.1.7. Set antenna for Tx
- 5.1.8. Set antenna for Rx
- 5.1.9. Start air Rx mode
- 5.1.10. Start continuous Tx mode
- 5.1.11. Query air Rx statistics
- 5.1.12. Reset air Tx/Rx statistics
- 5.2. Example Command
- 5.1. ATE Command
- 6. Flash Programing
- 7. Electrical parameters
- 8. Antenna Information
- 9. Assembly size and PCB package
- 10. Production Guidelines
- 11. FCC and IC Information
- 11.1. FCC Warning
- 11.2. IC warning
- 11.3. Trace antenna designs
- 11.4. RF exposure considerations
- 11.5. Antennas
- 11.6. Label and compliance information
- 11.7. Information on test modes and additional testing requirements5
- 11.8. Additional testing, Part 15 Subpart B disclaimer
- 11.9. The module is limited to OEM installation ONLY.
- 11.10. The OEM integrator is responsible for ensuring that the end-user has no manual instructions to remove or install module.
- 11.11. The module is limited to installation in mobile or fixed applications
- 12. Package and Label
- Appendix 1: Sales and Technical Support Information
EMC328x Series Wireless Module Data Manual
Copyright of Shanghai MXCHIP Information Technology Co., Ltd.
13
SPI Flash Memory
The CPU manages access to the flash memory from the I-Code and D-Code buses via the built-in SPI
Flash Control Unit (SPIC). At the same time, operations such as erasing, programming, and read-write
protection are implemented, and instruction prefetching and caching are used to accelerate the
execution of stored code on the flash memory.
PSRAM
Optional 4M byte PSRAM with 50MHz DDR memory.
System Storage Control Address Assignment
The address allocation is shown in Table 5:
Table 5 System Storage Space
Base Address
Top Address
Size
Function
Description
0x0000_0000
0x0001_FFFF
128KB
KM0 ITCM ROM (actually 96KB)
32MB: KM0 Memory Address
0x0002_0000
0x0002_7FFF
32KB
KM0 DTCM ROM (actually 16KB)
0x0002_8000
0x0007_FFFF
352KB
RSVD
0x0008_0000
0x0008_FFFF
64KB
KM0 SRAM
0x0009_0000
0x000B_FFFF
192KB
RSVD
0x000C_0000
0x000C_3FFF
16KB
Retention SRAM (1KB) (the same
port with KM0 SRAM)
0x000C_4000
0x000F_FFFF
240KB
RSVD
0x0010_0000
0x01FF_FFFF
31MB
RSVD
0x0200_0000
0x07FF_FFFF
96MB
External PSRAM
224MB: External Memory Address
0x0800_0000
0x0FFF_FFFF
128MB
External FLASH
0x1000_0000
0x1007_FFFF
512KB
KM4 SRAM
256MB: KM4 Memory Address
0x1008_0000
0x100D_FFFF
384KB
RSVD
0x100E_0000
0x100E_FFFF
64KB
Extension SRAM0 from Bluetooth
0x100F_0000
0x100F_FFFF
64KB
Extension SRAM1 from Wi-Fi
0x1010_0000
0x1013_FFFF
256KB
KM4 ITCM ROM
0x101C_0000
0x101D_7FFF
96KB
KM4 DTCM ROM
0x101E_0000
0x101F_FFFF
256KB
RSVD
0x1020_0000
0x1FFF_FFFF
254MB
RSVD
0x2000_0000
0x3FFF_FFFF
512MB
RSVD
Reserved
0x4000_0000
0x47FF_FFFF
128MB
KM4 Peripherals
128MB: KM4 Peripherals Address
0x4800_0000
0x4FFF_FFFF
128MB
KM0 Peripherals
128MB: KM0 Peripherals Address
0x5000_0000
0x57FF_FFFF
128MB
KM4 Peripherals Secure
128MB: KM4 Peripherals Secure
Address
0x5800_0000
0xFFFF_FFFF
2816MB
RSVD
Reserved
When developing firmware using the MXOS platform provided by MXCHIP, 4MB of Flash space is pre-
allocated as follows: