User's Manual

Smart Machine Smart Decision
SIM7500A_User Manual_V1.022016-09-29
6
Figure Index
Figure 1: SIM7500 series Block Diagram............................................................................................................. 9
Figure 2: Pin assignment overview...................................................................................................................... 11
Figure 3: Dimensions (Unit: mm)........................................................................................................................ 15
Figure 4: Footprint recommendation (Unit: mm)................................................................................................ 16
Figure 5: Power supply application circuit.......................................................................................................... 17
Figure 6: Linear regulator reference circuit......................................................................................................... 18
Figure 7: Switching modepower supply reference circuit................................................................................... 18
Figure 8: Reference Power on/offCircuit.............................................................................................................19
Figure 9: Power on timing sequence....................................................................................................................20
Figure 10: Power off timing sequence................................................................................................................. 21
Figure 11: Reference reset circuit........................................................................................................................ 22
Figure 12: UART full modem.............................................................................................................................. 23
Figure 13: UART null Modem.............................................................................................................................23
Figure 14: Reference circuit of level shift............................................................................................................23
Figure 15: RI behaviour（SMS and URC report）.............................................................................................24
Figure 16: RI behaviour（voice call）................................................................................................................24
Figure 17: USB reference circuit......................................................................................................................... 25
Figure 18: USIM interface reference circuit........................................................................................................ 26
Figure 19: Amphenol SIM card socket................................................................................................................ 27
Figure 20: PCM_SYNC timing............................................................................................................................28
Figure 21: EXT codec to module timing..............................................................................................................28
Figure 22: Module to EXT codec timing............................................................................................................. 29
Figure 23: Audio codec reference circuit............................................................................................................. 30
Figure 24: I2C reference circuit........................................................................................................................... 30
Figure 25: NETLIGHT reference circuit............................................................................................................. 31
Figure 26: ISINK reference circuit...................................................................................................................... 32
Figure 27: Antenna matching circuit (MAIN_ANT)........................................................................................... 35
Figure 28: Antenna matching circuit (DIV_ANT)...............................................................................................36
Figure 31: Top and bottom view of Module........................................................................................................ 41
Figure 32: Label Information............................................................................................................................... 41
Figure 33: The ramp-soak-spike Reflow Profile of Module................................................................................42
Figure 34: Packaging introduce........................................................................................................................... 44
Figure 35: Module tray drawing introduce.......................................................................................................... 44
Figure 36: Small carton drawing introduce..........................................................................................................45
Figure 37: Big carton drawing introduce............................................................................................................. 45
Figure 38: Reference design.................................................................................................................................46