User`s manual

BIOS SETUP
40 MB700 User’s Manual
Chipset Features Setup
This Setup menu controls the configuration of the chipset.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
SDRAM RAS-to-CAS Delay : 3 CPU Warning Temperature : 66°C/151°F
SDRAM RAS Precharge Time : 3 Current System Temp. : 41°C/ 105°F
SDRAM CAS Latency Time : 3 Current CPU Temp. : 27°C/ 80°F
SDRAM Precharge Control : Disabled Current CPU Fan Speed : 2789 RPM
DRAM Integrity Mode : Non-ECC Current Chassis Fan Speed : 2045 RPM
System BIOS Cacheable : Disabled VCCP (V)
:
1.98 V
VTT (V)
:
1.50 V
Video BIOS Cacheable : Disabled VCC3 (V)
:
3.45 V
+ 5 V
:
4.99 V
Video RAM Cacheable : Disabled +12 V
:
12.46 V
-12 V
:
-12.54V
8 Bit I/O Recovery Time : 3 -5V
:
- 5.
21 V
16 Bit I/O Recovery Time : 2
Memory Hole At 15MB-16MB : Disabled
Passive Release : Enabled
Delayed Transaction : Ensabled
AGP Aperture Size (MB) : 64
ESC : Quit á â à ß : Select Item
Auto Detect DIMM/PCI Clock : Disabled F1 : Help PU/PD/+/- : Modify
Spread Spectrum : Disabled F5 : Old Values (Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
SDRAM RAS-to-CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This field allows you to determine the timing of transition
from Row Address Strove (RAS) to Column Address Strobe (CAS). The
default setting is 3.
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to retain
data. The default setting is 3.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer. The default value is 3.
SDRAM Precharge Control
By default, the SDRAM Precharge Control field is set to Disabled.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH is cached, provided that the cache controller is
disabled.