Specifications

20ES1E AA 6.
Block Diagrams, Testpoint Overviews, and Waveforms
Block Diagram 3 Audio & Video
STROBE1N
STROBE1P
DATA1N
DATA 1P
STROBE3N
STROBE3P
DATA3N
DATA 3P
STROBE2N
STROBE2P
DATA2N
DATA 2P
HV_PRIM
HV_SEC
I2D1
I2D3
I2D2
FAST-
BLANK
FIFO
DMSD
CHR.
MUX
DE-
MUX
FAST
BLANK
SWITCH
FOR-
MATER
SYNC
2Fh
HV
INFO
HVSYNC
ADOC VIDDEC (PRI & SEC)
7300-J
DATA S YNC
SAMPLE RATE CONVERTER
AGC_AMP
Hor. TIMEBASE GEN.
DTO & CONTROL LOOP
SLOW START/STOP
L0W POWER STARTUP
1st
CONTROL
LOOP
SDAC
HIRES.
TIMING
GEN.
HOR. TIMEBASE GEN.
DTO & CONTROL LOOP
SLOW START/STOP
L0W POWER STARTUP
1st
CONTROL
LOOP
SDAC
HIRES.
TIMING
GEN.
ADC
2nd
CONTROL
LOOP
VERT.
WAVEFORM
EAST-WEST
WAVEFORM
VERT.
SAWTOOTH
VERT.
DRIVER
HDROUT
HFB
EHT
BCL
FBCIN
EWP
VDRP
VDRN
6365
3368 3367
ADOC DOP
PRI
SEC
SSIF
VIDDEC1
VIDDEC2
HVSYNC
SKIN
TONE
CONTROL
BLUE
STRETCH
GREEN
ENHANCE
RGB
MATRIX
FRAME
PROC.
PAN O-
RAMA
DCTI
SHARPNES
S
MEASURE
LTI
DYN.
PEAKING
F
I
L
T
E
R
LUMINANCE SHARPNESS
COLOUR FEATURES
Y
UV
Y
U
V
U
V
Y
Y
U
V
R
G
B
ADOC BEF
HOR.
COMPRESS
HOR.
COMPRESS
MAIN
CH.
SUB
CH.
VERT.
COMPRESS
SUB
FIFO
CACHE
NOISE
SHAPER
MAIN
FIFO
CACHE
NOISE
SHAPER
DNR
MEMORY
BUS
DEVICE
INTERF.
UNDI-
THER
UNDI-
THER
SCAN
RATE
CONVERT
OUTPUT
MUX.
UNDI-
THER
DISPLAY CONTROLMODE CONTROL
SDRAM
ADOC MBF
Y
UV
INPUT
SWITCH
MATRIX
BLACK
STRETCH
BLACK
STRETCH
HISTOG.
MODIFY
HISTOG.
MEAS.
BLACK
BAR DET.
BLACK
LEVEL DET
NOISE
MEAS.
MEASUREMENT
BLOCKS
VIDDEC1
VIDDEC2
MAIN
CH.
SUB
CH.
ADOC FEF
13.5 / 27 MHz
@ 720 ppl
27 / 54 MHz
@ 1440 ppl
LINEDRIVE1
HFB_X-RAY-PROT
FRAMEDRIVE+
FRAMEDRIVE-
VDDE
7730
7382
7393
3398
6397
6381
6382
6385
FLASH
X-PROT
+8V
EW_MPIF
(YUV)
(YUV)
(YUV)
(YUV)
Ext
Syn
c
Mux
SRC for
HFB1/
H-Sync
Sync
Mux.
H-2FH
V-2FH
FBL-SC1-IN
VDDCO
VDDE
VIDEO DECODER
POR_FLASH
EXT. STEREO
EXT. MONO
3380
3385
1,14,27
3,9,43,49
VDDE
VREF_DEFL
FEATURE BOX
SYNC & DEFLECTION PROCESSING
+5V2
+5V
+8V
+3V3
40
43
45
26
34
2
8
2
9
PROTECTION
B18
B2
B4
B7
B4
B11
31
EW-DRIVE
FROM
1116
B 5
B 6
B 8
B 9
3346
BPA
SDAC-VDDA
DOP-DTC-VDDA
DOP-DTC-VDD3
IMEAS-VDDA
SDAC-3V3
7300-I
TO BLOCK
DIAGRAM
DEFLECTION
2455
EHT-INFO
A3
A4
A4
FROM
BLOCK
DIAGRAM
STAND-BY
SUPPLY
A2
A8
0230
INTERFACING
A 6
VDD
VDDQ
FIELD MEMORY & TXT PG
DLINK-VDDA
DLINK-VDDD
VID1-DTC-VDDA
PLLVDDA
VID1-DTC-VDD3
7300-F
SAMPLE RATE
CO NVERTER
MEMORY
CTRL/SWI.
MMI BUS
SA0...SA11
SD0...SD15
DTL I/F
B6
B5
B8
B5
B7
TO
47
46
44
MEMORY INTERFACE
3350
7300 7300
7300
6353
3353
3354
+3V3
6367
7365
3372
TILT
VDDE
3340
3341
SEL2FH
VDDE
3387
3384
7383-B
7383-A
+8V
KEYBOARD
6384
A5
35
FROM
TUNER
SIMM
CONN.
TO
ROTATION
CIRCUITRY
5601
VDDE
B7
2397
7361
3364
3361
6368
+8V
3373
+5V
2361
VDDCO
B13
DMSD=Digital Multi Standard Decoder
DCTI=Digital Color
Transient Imrpovement
+3V3
EHT-INFO
EHT-INFO
F_15040_059.eps
290405