Specifications

Circuit Diagrams and PWB Layouts
41ES1E AA 7.
SSB: Video Decoder
2
I
D3
2
I
D2
( A-ADC1, A-ADC2 )
SSIF
EXT SUB MONO-CHANNEL
( A-ADC3 )
A-ADC4
SEC DECODER
TDC-
ANA
TDC-
DIG
SRC-YYUV-CYC
SRC-UYUV
SRC-VYUV
AMP-YYC
AMP-YYUV-CYC
AMP-UYUV
AMP-VYUV
AMP-SYNCYC SYNC-GAIN
CVBS-Y-GAIN
UV-GAIN
AGC
INCR
INCR
OVERFL.
DAV.
INCR
CVBS-YYC-DELTA
+DAV
UV-DELTA
+DAV
SYNC-GAIN
PRF-SYNC-2FH SYNC-
MODULE-
2FH
EXT-
SYNC
HSYNC-FBL+DELTA
HSYNC+DELTA
FBL+DELTA
COMB
YC DET
DEMUX
FBLANK
SWITCH
DMSD
FORMATTER
HV-INFO
Y
SYNC
FORMAT
H/V
REGISTER
AND
PI INTERF
BANDOUTS
VIDDEC-INT
PI-A
PI-D
EXT MAIN STEREO CHANNEL
I
2
DATA
SYNC
PRI DECODER
EXT
SYNC-
MUX
SRC-YYC
SRC
DELTA
GEN
FREQ-SELECT
DTO
ITS
DEC
FBLANK
FIFO
DELAY AND FAST-BLANK
’SRC’ FOR HFB1/H-SYNC
UV
D1
5283
100Mhz / 220R
B
5282 C95281 A9 I281 D23284 D2 5285 D95283 D9
2345
B2-44
78
3282 D2 3283 D2
B2-33
C
B2-31
B2-35
B2-34
B2-32
9
C
2
A
1
B2-37
B2-38
1
3
B2-36
B2-40
B2-39
6
5281
100Mhz / 220R
B2-41
B2-26
B18-45
B2-25
D
VIDEO DECODER
B2-42
3281 C1
54
2285 D92284 D9 F282 C2F281 D97300-J A3
8
100Mhz / 220R
100Mhz / 220R
B2-43
67 9
A
2281 A9 2282 C9
B
D
AE3PLLVSSA
N23VID1-DTC-VDD3
P23VID1-DTC-VDDA
N26VID1-DTC-VSSA
P24 VSYNC1
P25 VSYNC2
F281
H26 DLINK1DP
H23 DLINK1SN
H24 DLINK1SP
G24 DLINK2DN
G25 DLINK2DP
F24 DLINK2SN
F25 DLINK2SP
E25 DLINK3DN
E26 DLINK3DP
E23 DLINK3SN
E24 DLINK3SP
N24 HSYNCFBL1
N25 HSYNCFBL2
P26 HVINFO1
R23 HVINFO2
AF3PLLVDDA
ADOC
7300-J
F23DLINK-VDDA
D26DLINK-VDDD
G26DLINK-VSSA
J23DLINK-VSSD
H25 DLINK1DN
3283
1K
100n
2282
100n
VDDCO
2281
5282
VDDCO
VDDCO
5285
100n
2285
1K
3284
F282
1K
3281
3282
1K
VDDE
I281
2284
100n
HV_SEC
HV_PRM
STROBE1N
STROBE1P
DATA1N
DATA1P
STROBE3N
STROBE3P
DATA3N
DATA3P
STROBE2N
STROBE2P
DATA2N
DATA2P
FBL-SC1-IN
H-2FH
V-2FH
CL 36532058_026.eps
211103
3139 123 5536.2
3V2 DC