Service manual
DV-L70S
DV-L70BL
DV-L70W
20
9. IC FUNCTION LIST
9-1. IC201 MC44722A DIGITAL VIDEO ENCORDER
Pin No. Terminal name I/O Operation function
1 CVBS/Cb O Analog composite video signal output or Cb signal output current drive (positive)
2 CVBS/Cb O Analog composite video signal output or Cb signal output current drive (negative)
3 CVBS/Cb Vdd Power Supply for CVBS / Cb DAC circuit
4 Y O Analog luminance signal output current drive (positive)
5 Y O Analog luminance signal output current drive (negative)
6 YVdd Power Supply for Y DAC circuit
7 C/Cr O Analog chrominance signal output or Cr signal output current drive (positive)
8 C/Cr O Analog chrominance signal output or Cr signal output current drive (negative)
9 CVdd Power Supply for C/Cr DAC circuit
10 DA Vss Ground for DAC circuit
11 Ibias O Reference current for the 3 DACs
12 DA Vdd Power Supply for DAC circuit
13 VReff Reference full scale voltage for the 3 DACs
14 ChipA I2C chip address select {0 : 42(hex)/43(hex) 1 : 1C(hex)/1D(hex)}
15 TEST I TEST pin (Ground)
16 SO z(O) If SPI mode, serial data output / If I2C mode, connect to ground
17 SDA/SI I/O(I) Serial data input, Open drain output / If SPI mode, serial data input
18 SCL/SCK I Serial clock
19 SEL (I) Connect to Ground / If SPI mode, this pin is chip select
20 DVss Ground for Digital circuit
21 CLOCK I 27MHz clock input
22 DVdd Power Supply for Digital circuit
23 Reset I Reset signal, active LOW
24 PAL/NTSC I NTSC/PAL select. This pin active only Reset time.(NTSC : Low PAL : High)
25-32 DVIN7-0 I 8-bit Multiplexd Y/Cr/Cb 4:2:2 data (ITU Rec656) input (1) or Multiplexd Y data
(ITU-Rec656/601) input in 16-bit input mode (DVIN7 : MSB)
33 TVIN I TEST data input
34 EXT I/O Csync/Frame sync output or external VBI information input
35 F/Vsync I/O Frame sync or Vertical sync input/output
36 Hsync I/O Horizontal sync input/output
37 TP9 I/O MUX switch in 8-bit X 2 Multiplexed Y/Cr/Cb 4:2:2 data (ITU-Rec656) input mode,
or Test data input/output
38-41 TP8-5 I/O 8-bit Multiplexed 4:2:2 data (ITU-Rec656/601) input (2), or Multiplexed Cr/Cb data
(ITU-Rec656/601) input in 16-bit input mode (MSB : TP8), or Test data input/output
42 DVss Ground for Digital circuit
43 DVdd Power Supply for Digital circuit
44-47 TP4-1 I/O 8-bit Multiplexed 4:2:2 data (ITU-Rec656/601) input (2), or Multiplexed Cr/Cb data
(ITU-Rec656/601) input in 16-bit input mode (LSB : TP1), or Test data input/output
48 TP0 I/O For test (should be ground)
• Block Diagram
SO
SDA/SI
SCL/SCK
SEL
TEST
TP0~9
12C/SPI
16
17 18 19
24
23
21
37
33
DVIN
TVIN
TP9
clock
Reset
TP0~8
PAL/NTSC
48~44 41~38
DVIN0~7
32~25
ChipA
DVdd
DVdd
DVss
DVss
14
43
22
20
42
H, V
Y
demux
C
b
C
r
0
0
0
0
Modulator
off_set
+
+
0
0
0
CGM5_gen
CC_gen
Sync_generator
BG
34 35 36
EXT
F/Vsync
Hsync
copy
protection
bus
6
3
9
4
5
1
2
7
13
11
12
10
8
MC44722/3
15
TEST
BIAS
DAC
DAC
DAC
YVdd
CVBS/CbVDD
CVdd
YOUT
YOUT
CVBSOUT/Cb
CVBSOUT/Cb
COUT/Cr
COUT/Cr
VReff
Ibias
DAVdd
DAVss