Service manual

25
DV-L70S
DV-L70BL
DV-L70W
9-5. IC501 IX1697GE FLASH
Pin No. Symbol Type Name and function
Byte selection address: When the device is in the x8 mode, the low or high order
45 DQ
15
/A
-1
Input byte is selected. It is not used in the x16 mode.
(If BYTE# is high, DQ
15
/A
-1
input circuit does not operate.)
25, 24~18,
A
0
-A
12
Input
Word selection address: Selection of one word of 16k byte block. These addresses
8~4 are latched during data wiring operation.
3~15,
A
13
-A
17
Input
Block selection address: Selection of 1/32 erase block. These addresses are latched
48, 17 during data writing, erasing and lock block operation.
29, 31, 33, Low order byte data input/output: Command user interface writing cycle data and
35, 38, 40, DQ
0
-DQ
7
Input/Output commandinput. Various data read memory identifier and status data output Chip
42, 44 nonselection or output disable: Float state
30, 32, 34, 36,
DQ
8
-DQ
15
Input/Output
High order byte data input/output: The function is the same as that of low order byte
39, 41, 43, 45 data input/output. Operative only in x16 mode. x8 mode: Float state DQ
15
/A
-1
is address.
26 CE# Input
Chip enable: Device control logic, input buffer, decoder and sense amp. are activated.
Chip becomes active only when CE# is “Low”.
Reset/Power down: If RP# is set to “Low”, the control circuit is initialized when power is turned
on. Hence, the RP#pin is set to “Low”. When power is turned on or off or in case of fluctuation
12 RP# Input
it is kept at “Low” so as to protect data from noise.
When RP# is in “Low” state, the device is in deep power down state. 480 ns is required to
recover from the deep power down state. If the RP# pin becomes “Low”, the whole chip
operation is interrupted and reset. After recovery the device is set to array read state.
28 OE# Input
Output enable: When OE# is set to “Low”, data is output from the DQ pin. When
OE# is set to “High”, the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access
11 WE# Input is controlled. In “Low” state WE# becomes active. At rise edge the address and data
are fetched.
Ready/busy: The state of internal write state machine is output. In “Low” state it is
15 RY/BY# Output
indicated that the write state machine is in operation. If the write state machine waits for
next operation instruction, erase is suspended or it is in deep power down state, the RY/
BY# pin is in float state.
Byte enable: When BYTE# is set to “Low”, the device is set to the x8 mode. At this
47 BYTE# Input
time the DQ
8
-DQ
15
pin becomes float state. Address A
-1
selects high order/low order
byte. When BYTE# is “High”, the device is set to the x16 mode. The A
-1
input circuit is
disabled.
13 Vpp Write/erase power supply: 5.0 ± 0.5V is applied during writing/erasing.
37 Vcc Device power supply: 5.0 ± 0.5V
27, 46 GND Ground
9, 10, 14, 16 NC Nonconnection
ID
Register
CSR
ESRs
DQ
8-15
DQ
0-7
OUTPUT MULTIPLEXER
Program Erase
Voltage Switch
BYTE#
CUIWSM
16-KBYTE
Block 31
16-KBYTE
Block 30
16-KBYTE
Block 1
16-KBYTE
Block 0
CE#
OE#
WE#
RP#
RY/BY#
V
PP
V
CC
GND
Y GATING/SENSING
X-DECODER
Y-DECODER
Input
Buffer
ADDRESS
QUEUE
LATCHES
ADDRESS
COUNTER
A
-1.0~17
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
I/O Logic
DATA
QUEUE
REGISTER
Register
Data
Comparator
• Block Diagram