Service manual

UX-510UA
FO-1470U
[2] Circuit description of control PWB
1. General description
Fig. 2 shows the functional blocks of the control PWB, which is com-
posed of 5 blocks.
Fig. 2 Control PWB functional block diagram
2. Description of each block
(1) Main control block
The main control block is composed of CONEXANT 1 chip fax engine
(SCE114), ROM (2Mbit), SRAM (256kbit), DRAM (4Mbit) and Integrated
Analog (20415).
Devices are connected to the bus to control the whole unit.
1) SCE114 (IC9) : pin-176 QFP (FAX CONTROLLER)
2) 20415 (IC13) : pin-32 QFP (INTEGRATED ANALOG)
The FAX ENGINE Integrated Facsimile Controllers.
SCE114, contains an internal 8 bit microprocessor with an external 2
Mbyte address space and dedicated circuitry optimized for facsimile
image processing and facsimile machine control and monitoring.
3) 27L2000 (IC4): pin-32 DIP (ROM)
ROM of 2Mbit equipped with software for the main CPU.
4) W24258S-70LE (IC8): pin-28 SOP (SRAM)
Line memory for the main CPU system RAM area and coding/decoding
process. Used as the transmission buffer.
Memory of recorded data such as daily report and auto dials. When the
power is turned off, this memory is backed up by the lithium battery.
5) MSM51V4800E (IC5): pin-28 SOJ (DRAM)
Image memory for recording process.
• Memory for recording pixel data without paper.
Fig. 3
5 – 2
(3) ROM
(1) SCE114
(4) SRAM
MAIN CONTROL BLOCK MODEM BLOCK
(5) DRAM
(2) INTEGRATED
ANALOG (20415)
OPIF INPUTS
OPI[0]/GPIO[21]/SSRXD1
OPI[1]/GPIO[22]/SSSTAT1
OPI[2]/GPIO[23]/SSCLK1
OPI[3]/GPIO[24]
MC24 CPU CONTROL IF
MC24 MEGACALL(8-BIT DATA,24-BIT ADDRESS)
WATCHDOG TIMER
REAL TIME CLOCK
CRYSTAL OSCILLATOR
BATTERY BACK-UP CIRCUIT
INTERRUPT CONTROLLER
BUS INTERFACE
DRAM CONTROL
INTERNAL & EXTERNAL BUS CONTROL
INTERNAL & EXTERNAL DECODE
DMA CONTROLLER
OPERATOR PANEL IF
32 KEYS
8 LEDS
LCD MODULE
MOTOR POWER
CONTROL
RINGER
SSIF 1
THERMAL PRINTER IF
5 ms LINE TIME
A4/B4 LINES
TPH ADC
4 STROBE TPH
LATCHLESS TPH
EXTERNAL DMA I/F
T.4/T.6 CODEC
MH,MR,MMR
HARDWARE,ALTEMATE
COMPRESSION &
DECOMPRESSION
BI-LEVEL RESOLUTION
CONVERSION
PROGRAMMABLE
REDUCTION &
EXPANSION
4.4 KB VIDEO RAM
SCANNER CONTROL & VIDEO PROCESSING
8-BIT PADC
CCD/CIS SCANNER
5 ms,A4/B4 LINES
SHADING CORRECTION(1:1,1:8)
DITHERING
MULTILEVEL B4-A4 REDUCTION
ERROR DIFFUSION
MTF....ETC.
GENERAL I/O
ALTTONE
GPIO
CALLING PARTY
CONTROL
AUTOBAUD
SYNC-ASYNC SASIF
SSIF 2
FLASH MEMORY IF
CPU BUS
INTERNAL CPU BUS
EXTERNAL CPU BUS
DMA BUS
WRPROTN
SXOUT
TSTCLK
DEBUGN
RESETN
XIN
PWRDWNN
BATRSTN
SXIN
SEE
"OPIF
OUTPUTS"
BELOW
SEE
"OPIF
INPUTS"
BELOW
THADIN
PDAT
PLAT
STRB[3:0]
STRBPOL/
DMAREQ
PCLK/DMAACK
PWR/GND TEST
OPIF OUTPUTS
LEDCTL/GPO[16]
LCDCS/GPO[17]
OPO[0]/GPO[8]/SMPWRCTRL
OPO[1]/GPO[9]/PMPWRCTRL
OPO[2]/GPO[10]/RINGER
OPO[3]/GPO[11]
OPO[4]/GPO[12]/SSTXD1
OPO[5]/GPO[13]
OPO[6]/GPO[14]
OPO[7]/GPO[15]
ROMCSN
SYNC/GPO[20]
CLKCONFIG[0]/REGDMA/GPO[18]
CLKCONFIG[1]/WAITN/GPO[19]
RASN
CASN[1:0]
DWRN
CSN[0]
CSN[1]/GPO[21]
WRN
RDN
D[7:0]
A[23:0]
CLK1
CLK1N/GPO[25]
CLK2/GPO[24]
FCSN[2]/VIDCTL[1]/GPO[22]
FCSN[1]/VIDCTL[0]/GPO[26]
START
IVREFN
INTPWRDWNEN
FAX MODEM DSP
CORE (ML 94)
TONE GENERATOR
TONE
SA3IN/DSP1RQN
SR1IO
SA1CLK
SR4OUT
IA1CLK
IACLK/DSPCSN
IARESET
GPO[31]/SR3OUT
GPIO[0]/SR4IN
GPIO[1]/SASTXD
GPIO[9]/FRDN
GPIO[10]/SSSTAT2
GPIO[11]/BE/SERINP
GPIO[12]/CS2N
GPIO[13]/CS3N
GPIO[14]/CS4N
GPIO[15]/CS5N
GPIO[16]/IRQ8
GPIO[17]
GPIO[18]/IRQ9N
GPIO[19]/RDY/SEROUT
GPIO[20]/ALTTONE
SM[3:0/GPO[7:4]
PM[3:0/GPO[3:0]
GPIO[37]/IRQ15N
GPIO[36:25]
GPIO[30:26]
GPIO[2]/SASRXD
GPIO[3]/SASCLK
GPIO[4]/CPCIN
GPIO[5]/SSCLK2
GPIO[6]/SSTXD2
GPIO[7]/SSRXD2
GPIO[8]/FWRN
IVREFP
VREFP
VREFN/CLREF
VIN
XOUT