User`s guide

1/15/03 10-1
Chapter 10
UARTs
10.1 Theory of Operation
The LZ87010 has two UARTs, UART 0 and UART 1. UART 0 is 8051-compatible. UART 1
is almost identical to UART 0, except that in Modes 1 and 3, it derives its serial clock from
a dedicated baud rate generator, while UART 0 uses Timer 1.
10.1.1 Receive Operation
In modes 1-3, incoming data on the RXD0 or RXD1 pin is signaled by a start bit that pulls
the input LOW for one bit period. This is sampled on every cycle of a clock running at 16
times the UART’s baud rate. The falling edge of the start bit synchronizes the transfer with
a resolution of 1/16 of a bit period. The UART then samples the RXD0 or RXD1 pin during
each bit period until it accumulates an entire character. The transfer ends with a HIGH stop
bit. On a successful transfer, the serial data is copied into SBUF or SBUF1 (and, in 9-bit
modes, into the SCON.RB8 or SCON1.RB8 bit as well) and the receive interrupt bit
(SCON.RI or SCON1.RI) is set. If the RI bit is already set, indicating that a previous
transfer has not yet been serviced, the new serial data is discarded.
For greater noise immunity, each bit is sampled three times near the middle of the bit
period, at intervals of one 16x serial clock period. Whichever logic level is sampled at least
two of the three times will be the one used.
In Mode 0, there are no start or stop bits, and the character is 8 bits long. Mode 0 is a syn-
chronous mode in which the serial clock is provided on TXD0 or TXD1, and input data is
read on RXD0 or RXD1. The serial clock is provided by the LZ87010. The data rate is fixed
at one bit per PCLK cycle. A falling edge on TXD0 or TXD1 signals that a new data bit
should be written to RXD0 or RXD1. This bit is sampled at the rising edge of TXD0 or
TXD1. See Figure 10-1.
In the other modes, each character has one start bit and one stop bit. Mode 1 transfers 8
data bits; Modes 2 and 3 transfer 9 data bits. The lower 8 bits are stored in the SBUF reg-
ister (UART 0) or SBUF1 register (UART 1). The ninth bits are stored in the SCON.RB8 or
SCON1.RB8 register bits. See Figure 10-2.
There is one character of buffering on receive; the previous character can be read from the
SBUF or SBUF1 register (and, in nine-bit modes, SCON.RB8 or SCON1.RB8) at any time
before the next character is fully received.
The RXD0 and RXD1 pins are shared with general/purpose I/O ports. To prevent spurious
serial data from being received when the pin is not being used for that purpose, the receive
function of the UART can be disabled in the SCON (UART 0) or SCON1 (UART 1) register,
using the SCON.REN or SCON1.REN (receive enable) bits.