User`s guide

1/15/03 ix
List of Tables
Preface
Table 1. Register Name ..............................................................................................xvi
Table 2. Register Bit Fields .........................................................................................xvi
Chapter 1 – Introduction
Table 1-1. Signal Descriptions, Listed Alphabetically................................................. 1-5
Table 1-2. Interrupt Sources and Vectors ................................................................ 1-10
Table 1-3. Instruction Set Summary......................................................................... 1-18
Table 1-4. Operand Types ....................................................................................... 1-21
Table 1-5. Instructions’ Effect on Flag Bits...............................................................1-22
Table 1-6. Command Matrix..................................................................................... 1-23
Chapter 2 – System Clocking
Table 2-1. System Clock Signals ............................................................................... 2-5
Table 2-2. CLKCFG (Clock Configuration) Register .................................................. 2-6
Table 2-3. CLKCFG Register Fields........................................................................... 2-6
Table 2-4. CLKADC[2:0] Encoding............................................................................. 2-6
Table 2-5. CLKDIV[2:0] Encoding .............................................................................. 2-6
Table 2-6. PCON (Power Control) Register ............................................................... 2-7
Table 2-7. PCON Register Fields............................................................................... 2-7
Chapter 3 – 8051-Compatible Core
Table 3-1. Core Registers .......................................................................................... 3-1
Table 3-2. ACC (Accumulator) Register..................................................................... 3-2
Table 3-3. B Register ................................................................................................. 3-2
Table 3-4. DPH and DPH1 Registers......................................................................... 3-2
Table 3-5. DPL and DPL1 Registers..........................................................................3-2
Table 3-6. DPS Register ............................................................................................ 3-3
Table 3-7. DPS Register Bits ..................................................................................... 3-3
Table 3-8. PSW Register............................................................................................ 3-4
Table 3-9. PSW Register Bits..................................................................................... 3-4
Table 3-10. SP Register............................................................................................. 3-4
Chapter 5 – Internal Flash
Table 5-1. Approximate Flash Timing ........................................................................ 5-2
Table 5-2. FLASHCFG Register................................................................................. 5-3
Table 5-3. FLASHCFG Register Bits.......................................................................... 5-3
Table 5-4. FMOD Field Decoding............................................................................... 5-3
Table 5-5. FLASHTB Register.................................................................................... 5-4
Table 5-6. FLASHTB Register Bits............................................................................. 5-4