User`s guide

UARTs LZ87010 Advance User’s Guide
10-10 1/15/03
10.1.4 Serial Interrupts
The UARTs can generate both transmit and receive interrupts. Receive interrupts are gen-
erated at the end of the receive operation, which is when the last bit is sampled on the
RXD0 or RXD1 pin. This last bit is a stop bit except in Mode 0, when it is a data bit.
Transmit interrupts are generated when the last data bit has been transmitted to the TXD0
or TXD1 pin. Received data is available when the receive interrupt bit (RI) is set in the
SCON or SCON1 register.
The processor will call an interrupt routine if the interrupt is enabled. UART 0 has interrupt
vector 0x0023. Its interrupt is enabled setting the IE.ES interrupt enable bit. UART 1 has
interrupt vector 0x004B and is enabled by setting the IE1.IES0 interrupt enable bit.
The same vector is used by both transmit and receive interrupts. The interrupt handler deter-
mines which interrupts are pending by testing the RI and TI bits of the SCON or SCON1 reg-
ister. These bits must be cleared by the interrupt handler to clear the pending interrupt. In
particular, if RI is still set from a previous data transfer, any new received data transfers will
be discarded. This test of RI is made when the stop bit is received on a new character, which
means that the interrupt handler has one character time (ten or eleven bit periods, depending
on the serial mode) to process the previous character.
Table 10-2. UART 1 Baud Rate Example, Modes 1 and 3
BAUD
RATE
20 MHz XTAL 22.1184 MHz XTAL 40 MHz XTAL
BRGCNT Error BRGCNT Error BRGCNT Error
110 4,681 0.0% 6,283 0.0% 11,363
0.0%
134.5 4,646 0.0% 5,138 0.0% 9,293 0.0%
300 2,082 0.0% 2,303 0.0% 4,166 0.0%
600 1,041 0.0% 1,151 0.0% 2,082 0.0%
1,200 520 0.0% 575 0.0% 1041 0.0%
2,400 259 -0.2% 287 0.0% 520 0.0%
4,800 129 -0.2% 143 0.0% 259 -0.2%
9,600 64 -0.2% 71 0.0% 129 -0.2%
19,200 32 1.4% 35 0.0% 64 -0.2%
38,400 15 -1.7% 17 0.0% 32 1.4%
76,800 7 -1.7% 8 0.0% 15 -1.7%
115,200 4 -8.5% 5 0.0% 10 1.4%