User`s guide

UARTs LZ87010 Advance User’s Guide
10-14 1/15/03
10.3.3 BRGCNTH and BRGCNTL
(Baud Rate Generator Count) Registers
The UART 1 baud rate generator is implemented as an auto-reloading 16-bit countdown
time clocked by PCLK. When the counter rolls over, it is reloaded with the 16-bit value
in the BRGCNTH and BRGCNTL registers. The baud rate is determined by the
following equation:
Baud Rate = PCLK ÷ ((BRGCNTH,BRGCNTL) +1) × 16)
Loading BRGCNTL and BRGCNTH with 0xffff gives the minimum possible clock rate
(19 baud with a 40 MHz CCLK), and loading them with 0x0 gives the maximum baud rate
(1.25 Mbaud). UART1 will not function unless the ALTFEN1.UEN bit is set to ‘1’.
Table 10-9. BRGCNTH Register
BIT 7 6 5 4 3 2 1 0
FIELD CNT[15] CNT[14] CNT[13] CNT[12] CNT[11] CNT[10] CNT[9] CNT[8]
RESET 0000 0 000
RW RW RW RW RW RW RW RW RW
ADDR 0xC7
Table 10-10. BRGCNTL Register
BIT 7 6 5 4 3 2 1 0
FIELD CNT[7] CNT[6] CNT[5]] CNT[4] CNT[3] CNT[2] CNT[1] CNT[0]
RESET 0000 0 000
RW RW RW RW RW RW RW RW RW
ADDR 0xC6