User`s guide

1/15/03 11-1
Chapter 11
External Memory
11.1 Theory of Operation
The LZ87010 supports up to 64KB of external memory, using an interface bus consisting of
a 16-bit address bus (XMA[15:0]), an 8-bit data bus (XMD[7:0]), a write-enable signal
(nPSWR), and an output enable signal (nPSEN). This interface is suitable for glueless oper-
ation with asynchronous memory devices such as static RAMs, EPROMs, and EEPROMs.
At reset, Flash is enabled and external memory is disabled. External memory can replace
all or part of Flash memory by setting the XMCFG (external memory configuration) reg-
ister. If the Flash has been placed into Secure mode, however, the Flash is always
enabled, and no external memory accesses are possible. This is because the use of
external program memory is inconsistent with program security.
A programmable number of wait states is inserted between the assertion of the address
and the end of the transfer.
A block diagram of the LZ87010’s external memory interface is shown in Figure 11-1.
11.1.1 Writing to External Memory
External memory is mapped to the program memory space of the 8051-compatible core. In
the standard 8051 architecture, program memory is read-only. The LZ87010 implements
read/write access to both internal Flash memory and external memory through a new
instruction, MOVC (@DPTR++),A at opcode 0xA5. This instruction uses the Data Pointer
register to refer to a 16-bit address. The Data Pointer is auto-incremented after each write.
NOTE: Opcode 0xA5 is shared with another instruction, the software break command TRAP. The
MOVC (@DPTR++),A instruction is enabled when the TRAP_EN bit in the DPS register is ‘0’.
11.1.2 Reading from External Memory
While external memory is mapped as ‘program memory’, it can also be used for data
storage. It is read with the standard 8051 MOVC instruction and (as already described)
written with the MOVC (@DPTR++),A instruction.