User`s guide

LZ87010 Advance User’s Guide External Memory
1/15/03 11-5
11.4 External Memory Timing
When the LZ87010 reads data, the address is asserted first on XMA[15:0], followed by the
assertion of the output enable, nPSEN, as shown in Figure 11-2. nPSEN is asserted for
one cycle plus the number of wait states specified in the XMCFG register. Figure 11-3
shows a read with one wait state. The data on the XMD[7:0] pins is latched when nPSEN
is deasserted.
Writes involve the successive assertion of address (XMA[15:0]), data (XMD[7:0]), and
nPSWR, as shown in Figure 11-4. nPSWR is asserted for one cycle plus the number of
wait states specified in the XMCFG register. Figure 11-5 shows a write with one wait state.
The external memory device is expected to sample the data when nPSWR is deasserted.
As can be seen in Figure 11-2 through Figure 11-5, both reads and writes have a minimum
cycle time of 7 CCLK periods, which can be extended by wait states. The minimum access
time is 5 CCLK periods for both reads and writes.