User`s guide

1/15/03 12-1
Chapter 12
Interrupts
12.1 Theory of Operation
12.1.1 Interrupt-Related Registers
Many of the registers in the LZ87010 are interrupt-related, containing interrupt enable,
status, or priority bits. Table 12-1 is a list of registers with interrupt-related functions.
NOTE: *Registers with addresses ending in ‘8’ or ‘0’ are bit-addressable.
Table 12-1. Interrupt-Related Registers
NAME ADDRESS DESCRIPTION UNIT
ALTFEN1 0x95 Alternate Function Enables UARTs External Interrupts
ICSTATE 0xBF I
2
C Status I
2
C
IE 0xA8* Interrupt Enable
Interrupts
IE1 0xE8* Interrupt Enable 1
IP 0xB8* Interrupt Priority Control
IP1 0xF8* Interrupt Priority Control
IPH 0xB9 Interrupt Priority Control
IPH1 0xF9 Interrupt Priority Control
SCON 0x98* UART 0 Control
UARTs
SCON1 0xC8* UART 1 Control
T2CAP 0xD9 Timer 2 Capture Control Enhanced Timers
T2CMP 0xD3 Timer 2 Compare Control
T2CON 0xD1 Timer 2 Control
T2STA 0xD2 Timer 2 Status
T3CAP 0xE9 Timer 3 Capture Control
T3CMP 0xE3 Timer 3 Compare Control
T3CON 0xE1 Timer 3 Control
T3STA 0xE2 Timer 3 Status
T4CMP 0xF3 Timer 4 Compare Control
T4CON 0xF1 Timer 4 Control
T4STA 0xF2 Timer 4 Status
TCON 0x88* Timer/Counter 0 and 1 Control 8051-Compatible Timers
TMOD 0x89 Timer/Counter 0 and 1 Mode
WDTCTL 0xAC Watchdog Timer Control Watchdog Reset
WGCFG0 0xCC Waveform Generator 0 Configuration Waveform Generators
WGCFG1 0xCD Waveform Generator 1 Configureation