User`s guide

LZ87010 Advance User’s Guide Interrupts
1/15/03 12-5
12.1.4 Interrupt Priority
There are four interrupt priority levels, given as a two-bit quantity. The LSB is in IP or IP1,
while the MSB is in IPH or IPH1. For example, the Timer 0 interrupt priority LSB is in IP1
and its MSB is in IPH1. Interrupt 0b00 is the lowest priority and 0b11 is the highest. Note
that this is the reverse of the numbering scheme used for interrupt levels.
12.1.5 External Interrupts
External interrupts have two modes: level-triggered and edge-triggered (also called level-
sensitive and edge-sensitive). These are handled differently in both hardware and software.
With level-triggered interrupts, the interrupt is asserted by pulling one of the external inter-
rupt pins LOW. This signal is held LOW until the interrupt handler explicitly signals that it
be released, generally by dedicating I/O port pins as interrupt acknowledge outputs. Care
should be taken to ensure that an incoming interrupt cannot be dropped if it is asserted too
close to the acknowledge, and that, on the other hand, a single interrupt assertion will
never be serviced twice.
With edge-triggered interrupts, the interrupt is asserted by strobing the external interrupt
pin (a falling edge in the case of INT[0] or INT[1], and a rising edge in the case of INT[7:2]).
With edge-triggered interrupts, the interrupt source does not have to be cleared explicitly,
simplifying hardware design. The minimum pulse width for edge-triggered interrupts is two
PCLK cycles.
12.1.5.1 INT[0] and INT[1]
External interrupts 0 and 1 use the INT[0] and INT[1] pins. Each has its own interrupt vector
and status bit. These two interrupts are 8051-compatible. They can be individually
selected as being edge-triggered on a falling edge or level-triggered on a LOW level, using
the TCON.IT0 and TCON.IT1 bits.