User`s guide

LZ87010 Advance User’s Guide Interrupts
1/15/03 12-7
12.2 Signals
Table 12-4 shows the interrupt request signals in the LZ87010.
12.3 Registers
This section lists registers that deal primarily with interrupts. Many other registers have some
interrupt-related functions. These are listed in Table 12-1 and are covered in other chapters.
12.3.1 ALTFEN1 (Alternate Function Enable) Register
The ALTFEN1 (Alternate Function Enable) register enables and disables UART 1 and
selects between edge and level triggering on the INT[7:2] pins.
Table 12-4. Interrupt Signals
SIGNAL
NAME
SIGNAL
TYPE
PIN
NUMBER
PIN
TYPE
FUNCTIONAL UNIT
SHARED
WITH
DESCRIPTION
INT[7:0] I 83:76 I/O Interrupts P0[7:0] Interrupt Request Signals
Table 12-5. ALTFEN1 Register
BIT 7 6 5 4 3 2 1 0
FIELD /// /// /// /// /// UEN IE2 IT2
RESET 0 0 0 0 0 000
RW RW RW RW RW RW RW RO RW
ADDR 0x95
Table 12-6. ALTFEN1 Register Bits
BIT NAME DESCRIPTION
7:3 /// Reserved Reads return 0; write as 0.
2UENUART 1 Enable When ‘1’, UART 1 is enabled. When ‘0’, UART 1 is inactive.
1IE2
Interrupt Edge Flag When ‘interrupt 2’ (INT[7:2]) is set to be edge-sensitive
(ALTFEN1.IT2 = 1), this bit is set whenever the hardware detects a rising edge on
the OR function of INT[7:2]. It is cleared automatically upon entry to the interrupt
service routine. When INT[7:2] is set to be level-sensitive (ALTFEN1.IT2 = 0),
this bit always returns 0.
0IT2
Interrupt Trigger Mode This bit selects whether interrupt pins INT[7:2] are
level-sensitive or edge sensitive. If ‘1’, the interrupts are edge-sensitive and will be
asserted when a rising edge is detected on the OR function of INT[7:2]. If ‘0’, the
interrupts are level-sensitive and are asserted whenever any interrupt input in
INT[7:2] is LOW (that is, whenever a bitwise AND of INT[7:2] is zero).