User`s guide

Interrupts LZ87010 Advance User’s Guide
12-10 1/15/03
12.3.4 IP and IPH (Interrupt Priority) Registers
The IP and IPH (Interrupt Priority) registers set the priority of the standard 8051 interrupts.
Priority level is a two-bit number, with priority 0b00 being the lowest priority and 0b11 the
highest. The least-significant bits of the individual interrupt priorities are in the IP and IP1
registers, while the most-significant bits are in the IPH and IPH1 registers.
For example, to set a priority level of 0b10 for UART 0, IP.PS would be 0b0 and IPH.PS
would be 0b1.
Table 12-11. IP and IPH Register
BIT 7 6 5 4 3 2 1 0
FIELD /// /// /// PS PT1 PX1 PT0 PX0
RESET 0 0 0 0 0 000
RW RW RW RW RW RW RW RW RW
ADDR
IP: 0xB8
IPH: 0xB9
Table 12-12. IP, IPH Register Bits
BIT NAME DESCRIPTION
7:5 /// Reserved Reads return ‘0’; write as ‘0’.
4PSPriority for Serial Port 0
3PT1Priority for Timer 1
2PX1Priority for INT[1]
1PT0
Priority for Timer 0
0PX0
Priority for INT[0]