User`s guide

Analog Outputs (DAC) LZ87010 Advance User’s Guide
14-4 1/15/03
14.2 Signals
Table 14-1 details the DAC and waveform generator signals.
14.3 Registers
14.3.1 DACC (DAC Control) Register
The DACC (DAC Control) register contains power enable bits for both DACs. Powering
down the DACs when not in use reduces system power consumption.
Table 14-1. DAC Signals
SIGNAL
NAME
SIGNAL
TYPE
PIN
NUMBER
PIN
TYPE
FUNCTIONAL
UNIT
SHARED
WITH
DESCRIPTION
DA0 O 48 O DACs DAC 0 Analog Output
DA1 O 46 O DACs DAC 1 Analog Output
DAVREF I 49 I DACs
Voltage Reference for
Digital-to-Analog Converters
WFGIN0 I 66 I/O
Waveform
Generator
P3[5] Waveform Generator Clock Input 0
WFGIN1 I 65 I/O
Waveform
Generator
P3[4] Waveform Generator Clock Input 1
Table 14-2. DACC Register
BIT 7 6 5 4 3 2 1 0
FIELD PWEN1 /// /// /// PWEN0 /// /// ///
RESET 00000000
RW RW RW RW RW RW RW RW RW
ADDR 0xC4
Table 14-3. DACC Register Bits
BIT NAME DESCRIPTION
7PWEN1
Power Enable for DAC 1 Allows the DAC to be shut down when not in
use, conserving power.
0 = Off
1 = On
6:4 /// Reserved Reads ‘0’. Write as ‘0’.
3PWEN0
Power Enable for DAC 0 Allows the DAC to be shut down when not in
use, conserving power.
0 = Off
1 = On
2:0 /// Reserved Reads ‘0’. Write as ‘0’.