User`s guide

Analog Outputs (DAC) LZ87010 Advance User’s Guide
14-6 1/15/03
14.3.3 WGCFG0 and WGCFG1 (Configuration) Registers
The WGCFG0 and WGCFG1 (Waveform Generator Configuration) registers control the inter-
rupt interval (the number of waveform generator input clocks between interrupts) and the
memory step (the number of bytes added to the waveform generator index after an access).
Table 14-7. WGCFG0 and WGCFG1 Registers
BIT 7 6 5 4 3 2 1 0
FIELD /// IVL[2] IVL[1] IVL[0] /// STEP[2] STEP[1] STEP[0]
RESET 00010000
RW RW RW RW RW RW RW RW RW
ADDR
WGCFG0: 0xCC
WGCFG1: 0xCD
Table 14-8. WGCFG0 and WGCFG1 Register Bits
BIT NAME DESCRIPTION
7 /// Reserved Reads ‘0’. Write as ‘0’.
6:4 IVL[2:0]
Interrupt Interval Determines the number of input clock cycles before an
interrupt is generated. If IVL[2:0] is ‘0’, no interrupt is generated. The default is
an interrupt generated on every input clock cycle. See Table 14-9.
3 ///
Reserved Reads ‘0’. Write as ‘0’.
2:0 STEP[2:0]
Memory Step Determines the step value added to INDEX on each input
clock cycle. See Table 14-10.
Table 14-9. Waveform Generator Interrupt Intervals
IVL[2:0] INTERVAL
000 No Interrupt
001 1
010 2
011 4
100 8
101 16
110 32
111 64
Table 14-10. Waveform Generator Step Index
STEP[2:0] STEP SIZE
000 0
001 1
010 2
011 4
100 8
101 16
110 32
111 Reserved