User`s guide

1/15/03 15-1
Chapter 15
I
2
C Interface
15.1 Theory of Operation
The LZ87010 includes a two-wire I
2
C serial interface capable of operating in either Master
or Slave mode. The two wires are SCL (serial clock) and SDA (serial data). Both are open-
collector I/O pins.
The interface has a single byte of serial data buffering on receive and transmit. Registers
provide control over operating mode, serial clock frequency, and slave-mode address. A
debug register gives real-time status information about the interface, and a status register
contains status bits that remain set until cleared by software.
Interrupts are generated on a variety of conditions, and are vectored to address 0x0043.
They are enabled or disabled by the IE1.EI2C bit.
15.1.1 Setting I
2
C Clock Timing
When the I
2
C interface is in Master mode, the serial clock (SCL) is generated from PCLK,
using two registers, ICHCNT and ICLCNT for timing parameters. When the I
2
C interface
is in Slave mode, SCL is provided by the Master.
The equation for calculating the proper number of PCLKs required for setting the proper
SCL clock HIGH and LOW period is as follows:
H_CNT = ROUND_UP(MIN_SCL_HIGH
time
(µs) × PCLK(MHz)) – k)
L_CNT = ROUND_UP(MIN_SCL_LOW
time
(µs) × PCLK(MHz)) – k)
See Table 15-1 for the parameters for this equation. ‘ROUND_UP’ means to round all frac-
tions up to the next highest integer.
Table 15-1. I
2
C Clock Parameters
VALUE 400 Kbit/s 100 kbit/s
k43
MIN_SCL_HIGH 0.6 µs40 µs
MIN_SCL_LOW 1.3 µs4.7 µs