User`s guide

I
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C Interface
15-2 1/15/03
See Table 15-2 for sample calculations of the HIGH count. The LOW count is calculated
in the same way.
15.2 Interrupt Handling
In Slave mode, the I
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C interface handles address comparison, shifts data into or out of the
ICDATA register, and generates ACK pulses at the appropriate times. In short, the inter-
face hardware handles the bit-level operation of the protocol. In Master mode, the interface
also handles bus arbitration and synchronization.
The byte level and above are handled in software. Interrupts are generated on both receive
and transmit data, in a way similar to typical serial data interrupts. On transmit, when the
data in ICDATA has been sent and the interface is ready to accept another byte of transmit
data, a transmit interrupt is generated. On receive, when new data is received over the
interface and placed into the ICDATA register, a receive interrupt is generated.
For the purposes of interrupt generation, no distinction is made between address bytes
and data bytes. However, in Slave mode, the interface ignores transfers not addressed to
it. In 7-bit addressing mode, addresses that do not match that of the I
2
C interface do not
generate interrupts. Nor do any following data transactions.
In 10-bit addressing mode, the address is transferred in two bytes. If the first transfer (con-
taining the most-significant address bits) matches the most-significant bits of the Slave
address, an interrupt will be generated on both halves of the address. If the second part of
the address does not match, the ICSTAT.RX_ABRT bit is set, informing the interrupt han-
dler that the address was not a complete match.
In transmit mode, the ICCON must be updated on a byte-by-byte basis, because the
ICCON.S_TRNSFR bit must be set to ‘1’ to initiate a byte transfer. This register also con-
tains bits that set the operating mode.
In Master mode, bus arbitration and synchronization are handled in hardware. Addressing,
which was handled in hardware in Slave mode, is handled in software in Master mode. For
example, the R/W bit of a 7-bit address must be set in software; it is not overwritten by the
state of the R/W bit in the ICCON register.
Status bits in the ICSTAT and ICDBUG registers report the precise state of the interface.
For example, there are status bits reporting whether the current transfer is a Slave address
or if a transmit abort or receive data overrun has occurred.
Table 15-2. Sample I
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C HIGH Period Counts
I
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C DATA
RATE (kbit/s)
PCLK (MHz)
SCL HIGH
REQUIRED MIN. (␮s)
H_CNT
SCL HIGH
TIME (␮s)
100 6.6 4 24 4.09
100 9.9 4 37 4.14
400 10 0.6 2 0.60
400 15.3 0.6 6 0.654
400 20 0.6 8 0.66