User`s guide

I
2
C Interface
15-10 1/15/03
15.4.7 ICDBUG (I
2
C Debug) Register
The ICDBUG register holds real-time status about the current transfer.
Table 15-16. ICDBUG Register
BIT 7 6 5 4 3 2 1 0
FIELD /// /// I2C_W I2C_R ADDR DATA P_DET S_DET
RESET 00000000
RW RO RO RO RO RO RO RO RO
ADDR 0xBE
Table 15-17. ICDBUG Register Bits
BIT NAME DESCRIPTION
7:6 /// Reserved Reads ‘0’, write ‘0’.
5 I2C_W
Write in Progress Set to ‘1’ during write transfers on the I
2
C bus. This bit will be
cleared when the STOP condition is detected.
4I2C_R
Read in Progress Set to ‘1’ during read transfers on the I
2
C bus. This bit will be
cleared when the STOP condition is detected.
3 ADDR
Address Phase Set to ‘1’ when the addressing phase is active on the I
2
C bus.
This bit will set to ‘1’ at the beginning of the transfer (START phase) and cleared
to ‘0’ after the address phase has completed.
2DATA
Data Phase Set to ‘1’ when a byte of data is being read or written on the I
2
C bus.
This bit will remain ‘1’ until the transaction has completed.
1P_DET
STOP Detected Set to ‘1’ when a STOP Condition is detected. This bit will
remain ‘1’ until the ICDBUG Register is read by the processor.
0S_DET
START Detected Set to ‘1’ when a START Condition is detected. This bit will
remain ‘1’ until the ICDBUG Register is read by the processor.