User`s guide

LZ87010 Advance User’s Guide I
2
C Interface
1/15/03 15-11
15.4.8 ICSTAT (I
2
C Status) Register
The ICSTAT register gives status about the state of the interface.
Table 15-18. ICSTAT Register
BIT 7 6 5 4 3 2 1 0
FIELD SLV_ADDR RX_ABRT TX_ABRT IDLE 10_BIT_ADDR OVRFLW FULL_FLG INTR
RESET 0 0 00 0 0 00
RW RO RO RO RO RO RO RO RO
ADDR 0xBF
Table 15-19. ICSTAT Register Bits
BIT NAME DESCRIPTION
7 SLV_ADDR
Slave Address Set to ‘1’ when the last byte received on the I
2
C bus was
a Slave address byte.
6 RX_ABRT
Receive Abort In Slave mode, this bit will be set to ‘1’ if:
• The I
2
C interface is in 10-bit Slave mode and the upper address byte
matched but the lower address byte did not.
• In Master mode, this bit will be set to ‘1’ when the upper and lower
address bytes match and a restart was issued by the Master in a
Master-receive mode, but the repeated upper address does not match.
• When the OVRFLW bit is set to ‘1’ during the data phase of Slave-
receive mode. This bit will remain ‘1’ until the ICSTAT register is read by
the processor.
• When an address byte is received by the slave during the address
phase of Slave-receive and FULL_FLG is set.
5 TX_ABRT
Transmit Abort Set to ‘1’ when the I
2
C interface is operating in the
Master-transmitter mode and a Slave device does not respond with an
ACK signal after receiving a byte of data from the Master. It will also be set
to ‘1’ when arbitration is lost while operating as a Master. This bit will re-
main ‘1’ until the ICSTAT Register is read by the processor.
4IDLEIdle Set to ‘1’ when the I
2
C interface is not processing any messages.
3 10_BIT_ADDR
Ten-bit Address Set to ‘1’ when a 10-bit address is detected. This bit will
remain ‘1’ until the ICSTAT Register is read by the processor.
2OVRFLW
Overflow Set to ‘1’ if the first byte of data received on the I
2
C bus is not
read out of the ICDATA register before the next byte received is written
into the ICDATA register. The first byte written into the ICDATA register will
be lost. This bit will remain ‘1’ until the ICDATA Register is read.
1FULL_FLG
Full Flag Set to ‘1’, after a byte of address or data is received on the I
2
C
bus and written into the ICDATA register. This bit will remain ‘1’ until the
ICDATA Register is read by the processor or until the TX_ABRT bit is set.
0INTR
Interrupt Set to ‘1’ under the following conditions:
• After a data byte is received on the I
2
C bus and written to ICDATA
• After a Stop condition is detected.
• When either the FULL_FLG or OVRFLW flags are ‘1’
• In master mode, when the TX_ABRT flag is ‘1’
• In slave mode, when the RX_ABRT flag is ‘1’.
This bit will remain ‘1’ until reset by software.