User`s guide

LZ87010 Advance User’s Guide Introduction
1/15/03 1-7
NOTE: *The signal type is shown for each use of a multi-use pin. For example,
TXD0 and P3[1] share a pin. TXD0 is shown as O, while P3[1] is shown as I/O.
VDD_CORE PWR 67 PWR Power
Core Power Supply. Normally connected only to a
4.7 µF tantalum bypass capacitor.
VDDA PWR 47 PWR Power Analog Power, 3.3 V ± 10%. Must be derived from VDD
VSS GND 9, 42, 64 GND Power Digital Ground
VSSA GND 59 GND Power Analog Ground
WFGIN0 I 66 I/O
Waveform
Generator
P3[5] Waveform Generator Clock Input 0
WFGIN1 I 65 I/O
Waveform
Generator
P3[4] Waveform Generator Clock Input 1
XMA[15:8] O 25:18 O External Memory P2 External Memory Address Bus, Upper 8 Bits
XMA[7:0] O 35:28 I/O External Memory P8 External Memory Address Bus, Lower 8 Bits
XMD[7:0] I/O 17:10 I/O External Memory P5 External Memory Data Bus
XTAL_SUB1 I 72 I/O Clock
Crystal Oscillator Connection for 32 kHz subclock. If
an external clock generator is used, this pin is the
clock input.
XTAL_SUB2 O 73 I/O Clock
Crystal Oscillator Connection for 32 kHz subclock.
Connect to VSS if external clock generator is used.
XTAL1 I 74 I/O Clock
Crystal Oscillator Connection for High-Frequency
System Clock. If an external clock generator is used,
this pin is the clock input.
XTAL2 O 75 I/O Clock
Crystal Oscillator Connection for High-Frequency
System Clock. Connect to VSS if external clock gen-
erator is used.
Table 1-1. Signal Descriptions, Listed Alphabetically (Cont’d)
SIGNAL
NAME
SIGNAL
TYPE*
PIN
NO.
PIN
TYPE
FUNCTIONAL
UNIT
SHARED
WITH
DESCRIPTION