User`s guide

LZ87010 Advance User’s Guide Introduction
1/15/03 1-13
The active CPU clock source and clock divisor are chosen under software control. See
Figure 1-6. Three main clocks are derived from this divided clock:
• CCLK, the core clock, which runs at the divided clock frequency. CCLK halts in both Idle
and Stop modes.
• SCLK, the State Machine clock, which runs at the same frequency as CCLK. Unlike
CCLK, SCLK continues to run in Idle mode, halting only in Stop mode.
• PCLK, the peripheral clock, which runs at half the speed of SCLK. PLCK runs in Active
and Idle modes, and halts in Stop Mode.
Many of the peripherals, including the timers and UARTs, can perform additional clock
division. Some can choose either of the two input clocks independently of the SCLK
source. The ADC clock runs off the undivided system oscillator (XTAL1/XTAL2), applying
its own clock division.
Figure 1-6. Simplified System Clocking
LZ87010-86
SUB-CLOCK
OSCILLATOR
nEN
nEN
CLOCK
DIVIDER
IDLE
SCLK
CCLK
XTAL_SUB1
XTAL_SUB2
ADCCLK
ADC
CLOCK
DIVIDER
MUX
1
0
SEL
HIGH-
FREQUENCY
OSCILLATOR
STOP
XTAL1
XTAL2
DIVIDE
BY 2
PCLK
INTERNAL TO
THE LZ87010
EXTERNAL TO
THE LZ87010
HFCLK
SUBCLK