User`s guide

LZ87010 Advance User’s Guide Table of Contents
1/15/03 iii
Chapter 3 – 8051-Compatible Core
3.1 Theory of Operation ......................................................................................... 3-1
3.2 Registers .......................................................................................................... 3-1
3.2.1 ACC (Accumulator) Register ..................................................................... 3-2
3.2.2 B Register.................................................................................................. 3-2
3.2.3 DPH, DPL, DPH1, and DPL1 (Data Pointer) Registers............................. 3-2
3.2.4 DPS (Data Pointer Select) Register .......................................................... 3-3
3.2.5 PSW (Program Status Word) Register ...................................................... 3-4
3.2.6 SP (Stack Pointer) Register ...................................................................... 3-4
Chapter 4 – Internal RAM
4.1 Theory of Operation ......................................................................................... 4-1
4.1.1 Scratchpad RAM (256 Bytes).................................................................... 4-1
4.1.2 MOVX RAM (4,096 Bytes) ........................................................................ 4-2
4.1.3 Expansion.................................................................................................. 4-2
Chapter 5 – Internal Flash
5.1 Theory of Operation ......................................................................................... 5-1
5.1.1 The Info Array............................................................................................ 5-1
5.1.2 Flash Timing.............................................................................................. 5-2
5.1.3 Secure Mode ............................................................................................. 5-2
5.2 Registers .......................................................................................................... 5-3
5.2.1 FLASHCFG (Flash Configuration) Register .............................................. 5-3
5.2.2 FLASHTB (Flash Timebase) Register....................................................... 5-4
Chapter 6 – I/O Ports
6.1 Theory of Operation ......................................................................................... 6-2
6.1.1 General-Purpose I/O Ports........................................................................ 6-2
6.1.1.1 Idle and Stop-Mode Current ............................................................... 6-2
6.1.2 High-Current Output Ports......................................................................... 6-3
6.2 Signals.............................................................................................................. 6-4
6.3 Registers .......................................................................................................... 6-5
6.3.1 General-Purpose I/O Registers ................................................................. 6-5
6.3.2 High-Current Output Registers .................................................................. 6-6
Chapter 7 – 8051-Compatible Timers
7.1 Timer Theory of Operation ............................................................................... 7-1
7.1.1 Timer Modes ............................................................................................. 7-2
7.1.1.1 Mode 0................................................................................................ 7-2
7.1.1.2 Mode 1................................................................................................ 7-3
7.1.1.3 Mode 2................................................................................................ 7-4
7.1.1.4 Mode 3................................................................................................ 7-4
7.2 Timer 0 and Timer 1 Signals ............................................................................ 7-6
7.3 Timer 0 and 1 Registers................................................................................... 7-6
7.3.1 TCON (Timer 0 and 1 Control) Register.................................................... 7-6
7.3.2 TMOD (Timer 0 and 1 Mode) Registers .................................................... 7-7
7.3.3 Timer Data Registers (TH0, TH1, TL0, TL1) ............................................. 7-8