User`s guide

1/15/03 3-1
Chapter 3
8051-Compatible Core
3.1 Theory of Operation
The LZ87010 has an 8051-compatible core that supports the full instruction set of the 8051
architecture. It supports all the 8051 Special Function Registers (SFRs, called simply ‘reg-
isters’ in this document), plus a large number of additional functions.
The LZ87010 has a ‘machine cycle’ of only two clock cycles. That is, most instructions exe-
cute in two system clock (CCLK) cycles, compared with 12 cycles in the original 8051.
In addition to the increase in per-cycle performance, the LZ87010 core integrates many
special features, including on-chip hardware debugging features, four levels of interrupt
priority, Watchdog reset timer, and many more. These features are covered in their
respective chapters.
3.2 Registers
Most registers are associated with functional units covered in other chapters. For example,
the SBUF (Serial Data Buffer) register is covered in the UART chapter. The descriptions
of such registers are not repeated here.
NOTE: *Registers marked with an asterisk (*) are bit-addressable.
Table 3-1. Core Registers
NAME ADDRESS* DESCRIPTION
ACC 0xE0* Accumulator
B 0xF0* B Register
DPH 0x83 Data Pointer [15:8]
DPH1 0x85 Data Pointer 1 [15:8]
DPL 0x82 Data Pointer [7:0]
DPL1 0x84 Data Pointer 1 [7:0]
DPS 0x86 Data Pointer Select and Extended Operation
PSW 0xD0* Program Status Word
SP 0x81 Stack Pointer